20-bit single-chip audio digital-to-analog converter PCM63P

1 Overview

PCM63P is an ultra-low distortion 20-bit precision DAC chip produced by BB using a unique dual DAC co-linear structure. This structure can eliminate harmful digital-analog inductive interference errors and other nonlinearities near the bipolar zero point. Therefore, the noise of PCM63P is very low (the maximum SNR is 116dB), and it also has a 16-fold oversampling rate and a fast settling time of 200ns for a 2mA step current output. The following are the main features of PCM63P:

●It is a co-linear 20-bit audio DAC;

●Can work at low level almost ideally;

● Output numerous modes of inductive interference;

●Fast (200ns) current output (±2ms);

●With industrial standard serial input interface; ●Ultra-low distortion, maximum -96dB (without external adjustment);

●With reference source;

●The minimum SNR is 116dB (calculated in a weighted manner);

●With 16 times oversampling capability.

2 Structure and function

Figure 1 shows the internal structure of the PCM63P digital-to-analog converter chip. Figure 2 shows its pin arrangement. The functions of each pin are described as follows:

CAP (pin 1): servo amplifier decoupling capacitor access terminal;

+VA (pin 2): +5V analog power supply;

CAP (pin 3): reference decoupling capacitor access terminal;

CAP (pin 4): offset decoupling capacitor terminal;

BPO (pin 5): Bipolar bias current output port, typical bias current output is +2mA;

IOUT (pin 6): DAC current output;

ACOM (pin 7): analog common terminal;

RF1 (pin 9): feedback access terminal;

RF2 (pin 10): A 1.5kΩ feedback resistor is connected between this pin and pin 9 inside the chip for external feedback;

-VD (pin 11): -5V digital power supply;

DCOM (pin 12): digital common terminal; [page]

+VD (pin 13): +5V digital power supply;

CLK (pin 18): DAC data clock input;

LE (pin 20): DAC data latch enable;

DATA (pin 21): DAC data output;

UB2 Adj (pin 23): select high DAC bit 2 adjustment (-4.29V);

LB2 Adj (pin 24): select low DAC bit 2 adjustment (-4.29V);

VPOT (pin 25): adjust the reference voltage tap (-3.25V);

-VA (pin 28): -5V analog power supply;

NC (other): No foot.

3 Working Principle

3.1 Dual DAC Colinear Structure

The PCM63P uses a new design. It combines the advantages of traditional DACs (good full-scale performance, high signal-to-noise ratio and ease of use) with excellent low-level performance. The two DACs inside are combined in a complementary manner to produce good linear output. The two DACs share the reference source and the R-2R ladder network, thereby ensuring complete tracking under all conditions. They achieve high-precision matching between DACs by exchanging individual bits of the DACs and laser-calibrated precision resistors. This new complementary linear structure used by the PCM63P is also called a dual DAC colinear structure. This structure can leave the zero point with small steps in both directions, thereby avoiding any misoperation or "large" linear errors, while providing an absolute current output. The low-level performance of the PCM63P ensures its 20-bit accuracy, especially near the critical bipolar zero point.

3.2 Dynamic indicators

An important dynamic indicator of the PCM63P is the total harmonic distortion + noise (THD + N). The PCM63P reads in digital data at 8 times the standard audio sampling frequency of 44.1kHz, thereby achieving a sine wave output of 991Hz. The dynamic range of its audio conversion can be seen as the measured value of THD + N at a -60dB effective output signal level relative to 0dB. At a -90dB output level, the PCM63P's deviation from the ideal signal is generally less than ±0.3dB. These performances reflect the PCM63P's collinear DAC circuit's near-ideal performance in the low noise and bipolar zero area.

4 Applications of PCM63P

4.1 Digital Input

PCM63P can receive logic levels compatible with TTL. On the input line, the logic input structure of differential current mode improves the anti-noise interference ability of PCM63P. The data format of PCM63P adopts binary complement format, which is a serial data stream with the most significant bit in front. Any number in the bit string can be loaded before 20 bits of data, because after LE (register enable signal) becomes low, only the last 20 bits of data before it can be transferred to the parallel DAC register.

In the PCM63P chip, the serial data input bits of the DAC are triggered on the rising edge of the clock CLK, and the conversion of the DAC serial to parallel data is performed on the falling edge of the enable signal LE. The conversion timing diagram is shown in Figure 3. The typical clock rate of the PCM63P is 16.9 MHz.