Migrating 8051 Applications to ARM Cortex-M Processors

The Cortex-M processor series includes the widely used Cortex-M3 processor, the Cortex-M1 processor for FPGA, the Cortex-M0 processor (the smallest ARM processor) launched in early 2009, and the Cortex-M4 processor (supporting floating-point and digital signal processing enhanced instructions) launched in early 2010. These processors have advanced features and easy-to-use programming models, which are very attractive to developers who want to migrate from 8051 microcontrollers to the ARM architecture. This article is an introductory guide to help developers of 8051 microcontrollers understand the main differences in architecture, software and hardware design between 8051 and ARM Cortex-M processor series, thereby accelerating the migration process.

Architecture Overview

For some embedded programmers (especially those who are accustomed to programming in assembly language), the first thing to do is to understand the programming model.

register

The ARM Cortex-M processor has one 32-bit register bank and one xPSR (Combined Program Status Register). The 8051 has ACC (Accumulator), B, DPTR (Data Pointer), P SW (Processor Status Word) and four register banks of eight registers each (R0-R7).

In 8051, some instructions frequently use certain registers, such as ACC and DPTR.

This correlation will greatly reduce the performance of the system. In ARM processors, instructions can use different registers for data processing, memory access and as memory pointers, so this problem does not exist.

Fundamentally, the ARM architecture is a RISC architecture based on load and store, where the processor registers load data and then pass the data to the ALU for single-cycle execution. The 8051 registers (ACC, B, PSW, SP, and DPTR) can be accessed in the memory space of the SFR (Special Function Register).

To ensure that ordinary C functions can be used as interrupt handlers, the Cortex-M registers (R0 - R3, R12, LR, PC, and xPSR) are automatically pushed onto the stack when an interrupt needs to be handled, and software only needs to push other registers onto the stack when necessary. Although the 8051 has 4 register banks, the ACC, B, DPTR, and PSW registers are not automatically pushed onto the stack, so these registers usually need to be pushed by software through the interrupt handler.

register

ARM processors have 32-bit addressing, which can implement a 4GB linear memory space. This memory space is structurally divided into multiple areas. Each area has its own recommended usage (although it is not fixed). The unified memory architecture not only increases the flexibility of memory usage, but also reduces the complexity of using different data types in different memory spaces.

In contrast, the 8051 microcontroller has multiple memory spaces. The segmentation of the memory space makes it difficult to use all the memory space efficiently, and requires the use of C language extensions to handle different memory types.

8051 supports up to *KB of program memory and 64KB of data memory in the external RAM memory space. In theory, the program memory size can be expanded by using memory paging. However, the memory paging solution is not standardized. In other words, the implementation of memory paging by different 8051 vendors is not the same. This not only increases the complexity of software development, but also significantly reduces software performance due to the software overhead required to handle page switching.

On the AMC or tex-M3 or M4, both the SRAM area and the peripheral area provide a 1MB bit band region (bit band regiON). This bit band region allows access to each bit inside it through an alias address. Since the bit band alias address can be accessed through ordinary memory access instructions, the C language can fully support it without any special instructions. The 8051 provides a small amount of bit addressable memory (16 bytes on the internal RAM and 16 bytes on the SFR space). Special instructions are required to process these bit data, and to support this function, a C language extension is required in the C compiler.

The memory map of the ARM Cortex-M processor contains several built-in peripheral blocks. For example, one of the features of the ARM Cortex-M processor is a nested vector interrupt controller (NVIC). In addition, the system area memory map has several designated control registers and debug components to ensure excellent interrupt handling and greatly facilitate the use of developers. [page]

Stack Memory

Stack memory operation is an important part of the memory architecture. In 8051, the stack pointer is only 8 bits, and the stack is located in the internal memory space (up to 256 bytes, shared by the working registers (four register banks consisting of R0 to R7 each) and internal data variables). Stack operation is based on the empty increment model.

Unlike the 8051, the ARM Cortex-M processor uses system memory as a stack, using a full-down model.

The full descending stack memory model is more supported by the C language. For example, the use of SRAM in a microcontroller can be organized as:

C libraries and applications that use dynamically allocated memory space usually require heap memory.

Although the Cortex-M processor requires 32 bits of stack memory for each push, the total RAM usage is still smaller than that of the 8051. 8051 variables are usually statically placed on IDATA, while the local variables of the ARM processor are placed on the stack memory, so local variables only occupy RAM space when the function is executed.

In addition, the ARM Cortex-M processor provides a second stack pointer to allow the operating system kernel and process stack to use different stack memories. This makes operation more reliable and makes the operating system design more efficient. (Stack pointer switching is handled automatically) Many peripherals in the 8051 are controlled by special function registers (SFRs). Since the SFR space is only 128 bytes, and some of it is already occupied by processor registers and standard peripherals, the remaining SFR address space is usually very limited, thus limiting the number of peripherals that can be controlled through SFRs. Although peripherals can be controlled through external memory space, external access usually requires more overhead than SFR access (addresses need to be copied to DPTR and data must be transferred through ACC).