Three-phase five-level inverter PWM pulse generator using DSP and CPLD

1 Introduction

In recent years, multilevel converters have become one of the hot topics in power electronics research, mainly targeting medium voltage and high power applications. Currently, there are three basic multilevel converter topologies [1]: ① diode clamp type; ② flying capacitor type; ③ cascade type.

Several topological structures have their own advantages and disadvantages, but relatively speaking, the cascade multilevel inverter has more unique advantages, and its structure is shown in Figure 1. It does not require clamping diodes and capacitors, is easy to package, does not have the problem of capacitor voltage balance, and can be used to realize the WM pulse generator.

2 Carrier Phase Shift SPWM Technology

The so-called phase-shifted PWM technology is to keep the frequencies of the modulation wave and the carrier wave fixed, and the phase of the modulation wave constant, while only adjusting the phase of the carrier wave to generate an SPWM signal. The SPWM signals under different carrier phases are linearly combined to achieve the purpose of eliminating harmonics and increasing output power. It can be proved that when the phase is shifted (α is the phase shift angle of the carrier wave of each unit with the same phase, and N is the number of cascaded units) [2], the output harmonic frequency increases to 2N times, which is easier to filter out. For a three-phase five-level inverter, N=2, so the carrier waves of the two cascaded units with the same phase differ by 90 degrees. As shown in Figure 2, A11 and

Figure 2 Phase A of a three-phase five-level inverter

The carriers of A14 are 180 degrees apart, the carriers of A11 and A21 are 90 degrees apart, and the carriers of A21 and A24 are 180 degrees apart. The output voltage after A1 and A2 are connected in series is:

From formula (1), we can see that UA no longer contains harmonics below 2F±1, but only contains harmonics above 2F±1. When the cascade number is N, all harmonics below NF±1 are filtered out.

3 Principle of PWM pulse generator for three-phase five-level inverter based on CPLD

A DSP can only generate 12 PWM pulses, while a three-phase five-level inverter requires 24 PWM pulses. When using dual DSPs to output 24 pulses, there is a problem of simultaneity, so complex programmable logic devices (CPLDs) are used to achieve this. Currently, complex programmable logic devices (CPLDs) have become an indispensable device in modern digital circuit design. The number of logic gates contained in CPLDs ranges from hundreds to tens of thousands, and they have hundreds of registers and I/O ports that can be arbitrarily configured. In addition, they have a short development cycle and can be flexibly configured to achieve multiple functions without changing the hardware circuit. [page]

Figure 3 is a control block diagram of a PWM pulse generator composed of DSP and CPLD.