System-on-chip design and static timing analysis

1 Introduction
Today, as integrated circuit design technology has entered the fourth generation, an electronic system or subsystem can be fully integrated on a chip, that is, system-on-chip (SOC) integration. As the design scale increases, circuit performance improves, and the complexity of design increases, higher requirements are placed on the design methodology accordingly. In
traditional chip design, only the delay of the gate itself is considered, and the delay caused by the interconnection is negligible. For this reason, the traditional design process can be divided into two independent stages: logic design and physical implementation, and the chip design considerations are relatively simple. As the size of transistors decreases, the speed of gates becomes faster and faster. The main factor limiting the improvement of circuit performance is no longer the switching speed, but the interconnection delay. The higher the clock frequency, the greater the proportion of the delay caused by the interconnection line as a fan-out load in the entire timing budget. In the deep submicron design range, the interconnection delay accounts for 60% to 70% of the total delay, so it is very important to accurately calculate this part of the delay in chip design. At the same time, high-performance circuits make the tolerance of all timing very small, and also put forward higher requirements for accurately positioning the delay model of each part of the circuit. On the other hand, since the interconnection delay information can only be obtained after physical implementation during the implementation of EDA (electronic design automation) tools, in deep submicron chip design, accurate timing can only be obtained by constraining the logic design with actual layout topology information. Therefore, in order to improve chip design efficiency and shorten the design cycle, system-on-chip chip design (often using deep submicron technology) must overcome the drawbacks of the separation of front-end design and back-end design in traditional design methods.
In addition, since the previously popular dynamic timing verification verifies the timing while verifying the function, input vectors are required as incentives. As the scale increases, the number of vectors required increases exponentially, and the time required for verification accounts for 50% of the entire design cycle. In addition, this method is difficult to ensure sufficient coverage, so it has become a bottleneck in the design process for system-on-chip chip design, so it must be replaced by a more effective timing verification technology.

2 Design process of system-on-chip chips
In the integration of system-on-chip, DSP or CPU core design methods are increasingly used, which has been highly valued by EDA experts and scholars from all over the world. The design of SOC involves three aspects: algorithm, software and hardware. Software-hardware co-design technology allows software and hardware testing in the early stage of design, and early discovery of design problems, so it has become a current research hotspot. However, the software-hardware co-design method at the system level still needs further in-depth research. Because according to the existing general software-hardware co-design method, after determining the system structure and completing the division of software and hardware, the behavior model, RTL-level hardware language description and data channel synthesis method are used to complete the hardware design, and the software is implemented by manual assembly and compiler. The important parameters of the system are obtained through the co-simulation of the software-hardware division. Therefore, the determination of the system structure is very critical, but due to the diversity of system models, it is impossible to exhaust all possible situations, nor can it establish a good model design strategy at the system level. In this way, the results of lower-level software and hardware optimization are difficult to ensure that they fully meet the goal of the entire system optimization. For high-level automated synthesis, the method adopted by general automated tools is to first establish a control data flow diagram based on the functional description of the system, and then obtain a suitable data path through scheduling and positioning. This method is effective for systems with a low number of operations and a small number of functional units on the chip. However, for system chips such as MPEG encoders, due to the huge amount of operations, there may be dozens of functional units on the chip. It is impossible to use a fully automated method to schedule and map hardware between so many operations and units. In addition, the software simulation time is also very long in the automated verification process. Therefore, for the design of highly complex system-on-chips, software and hardware co-design strategies must be developed at a higher level of abstraction. The implementation process of
the system-on-chip on EDA tools has also become more complicated accordingly. As the feature size decreases, the delay of the device itself continues to decrease (0.1um CMOS circuit, the typical gate delay is 11.8ps). At the same time, since the resistance of the interconnection line per unit length continues to increase with the reduction of the feature size, the line delay caused by the interconnection line resistance and line capacitance continues to increase. When it is below 0.35um, the interconnection delay can even reach 90% of the signal delay. Therefore, when the system-on-chip chip is implemented on the EDA tool, the influence of the interconnection after layout must be considered while performing the front-end design.

3 Static Timing Analysis
Simulation technology is the most widely used verification method in the ASIC design process. However, the current monolithic integrated system design is pushing the simulation time to an intolerable limit. In the final gate-level simulation stage, the circuit is tens or even millions of gates. The first requirement for the simulator is speed and capacity. Therefore, performance (simulation speed) and capacity (the design scale that can be simulated) are key factors in verification. At this time, the simulator must also support SDF return and timing check to ensure the accuracy of verification.
Traditionally, logic simulators are used to verify functional timing, that is, to verify timing while verifying functions. It runs in a logic simulation mode and requires input vectors as stimulus. As the scale increases, the number of vectors required increases exponentially, and the time required for verification accounts for 50% of the entire design cycle. The biggest problem is that it is difficult to ensure sufficient coverage. In view of this, this method has been used less and less for timing verification, and has been replaced by static timing analysis technology.
Static timing analysis technology is an exhaustive analysis method used to measure circuit performance. It extracts all the timing paths of the entire circuit, finds out the errors that violate the timing constraints by calculating the delay propagation of the signal along the path, and mainly checks whether the setup time and hold time meet the requirements, which are obtained by analyzing the maximum path delay and the minimum path delay respectively. The static timing analysis method does not rely on stimulus, and can exhaust all paths, runs very fast, and occupies very little memory. It completely overcomes the defects of dynamic timing verification, is suitable for the verification of ultra-large-scale system-on-chip circuits, and can save up to 20% of the design time. Therefore, the static timing analyzer meets the purpose of full-chip analysis in terms of function and performance. Supporting system-on-chip design, that is, it has made a breakthrough in meeting the design timing requirements quickly, can provide the performance required by million-gate design, and analyze the design in a reasonable time, and it has advanced timing analysis technology and visualization features for full-chip verification.

4 Design Examples and Experimental Results
We studied the MPEG encoding chip system, which is a highly complex electronic system. Figure 2 shows its structure, which contains two programmable ASIPs of different natures: the high-level is a programmable RISC core (see Figure 3 for structure), which mainly completes the algorithmic tasks of variable-length coding in addition to coordinating the operations of various parts; the low-level is a high-throughput programmable digital signal processor DSP core, which is mainly used for fine-grained algorithmic tasks such as motion estimation, discrete cosine transform and quantization. In addition, there is a dedicated DMA (Direct Memory Access) controller inside the encoder to manage the data exchange between on-chip memory and off-chip memory units. Here, we focus on the structural design of the embedded RISC core on the system chip, its implementation on EDA tools, and static timing analysis.
The study shows that the RISC core can complete the variable-length coding task of MPEG-2 at a clock frequency of 50MHz.
We use EUROPRACTICE's 0.35μm CMOS low-power library MTC45000 series, on the Ultra SUN workstation, introduce Cadence's Floorplanning tool to plan the layout as a whole, and Synopsys Synthesis tool to perform logic synthesis. The design is carried out according to the design flow in Figure 1, in which Synopsys's PrimeTime is used to analyze the gate-level static timing of the entire chip and complete the static timing verification of the SOC design.
The comprehensive optimization results show that the circuit scale of the RISC core is about 5500 gates (16 general registers), the dynamic power consumption is 20mW, and the clock frequency is 73MHz. The RISC core fully meets the expected design goals. Table 1 shows the report generated by the static timing analysis of the critical path using Synopsys's PrimeTime tool (verification of the establishment time). The results show that the path meets the requirements. It should be pointed out that static timing analysis technology is an exhaustive analysis method that extracts all timing paths of the entire circuit. Due to space limitations, this article will not explain and list them one by one.

5 Conclusion
This paper emphasizes that the impact of back-end layout on timing must be considered in the front-end design process of the SoC design process, and a new, full-chip, gate-level static timing analysis tool is used to support SoC design, avoiding the phenomenon of silicon chip failure due to incomplete chip design verification. The example design shows that this design method can improve the accuracy of timing design in SoC chip design, improve verification efficiency, and thus greatly accelerate the convergence of the design.