Interface Design between S3C44B0X and C54X DSP

1: Introduction to S3C4510B

S3C4510B (hereinafter referred to as 4510) is a 16/32-bit high-performance microprocessor based on ARM7TDMI architecture developed by Samsung, South Korea. It has rich peripheral interfaces, such as Ethernet, HDLC, etc., and can be flexibly configured for a variety of applications. 4510 has the following performance characteristics:

◆ 8K bytes of internal cache, which can also be used as internal SRAM

◆ Two-wire IIC interface, used as IIC master device

◆ Ethernet controller

◆ Dual channel HDLC controller

◆ Dual UART

◆ Dual GDMA channels

◆ Two 32-bit timers

◆ 18 programmable IO ports

◆ Interrupt control function

◆ External SDRAM/DRAM/FLASH/ROM control

This article mainly introduces the use and programming methods of HDLC channels in 4510.

2: Introduction to HDLC Channel of S3C4510B

For the HDLC protocol frame structure and characteristics, please refer to relevant books and 4510 data manuals, which will not be introduced in detail here.

The HDLC channel structure of 4510 is shown in Figure 1. It has the following characteristics:

1. FIFO: Both the sending and receiving modules have 32-byte (8-word) FIFOs, which provide data buffering function between the CPU internal bus and the HDLC serial interface.

2. DMA: The sending and receiving of HDLC channel supports DMA mode.

3. Baud rate generation: The 4510's HDLC channel contains a programmable baud rate generation counter that can generate a variety of baud rate transmission rates.

4. DPLL: The 4510's HDLC channel contains a digital phase-locked loop (DPLL) that provides a clock recovery function that can quickly extract clock information from the encoded data stream.

5. Coding mode: The HDLC channel of 4510 supports five coding modes, namely NRZ, NRZI, FM0, FM1 and differential Manchester coding. Please refer to Figure 2 for the coding waveform.

For more details, please refer to the 4510 data sheet.

3: Introduction to the working process of S3C4510B HDLC channel

The HDLC channel of 4510 can work in CPU mode and DMA mode. In our application and programming, we use DMA mode, so here we mainly introduce the working process under DMA mode. The working process of 4510 HDLC channel can be roughly divided into three parts: channel initialization, data transmission and data reception.

3.1: HDLC channel initialization process

The HDLC channel initialization process can be divided into seven steps: 1. Reset the channel and restore its default configuration; 2. Configure the HDLC working mode by setting the working mode register (HMODE); 3. Control the operation of the HDLC channel by setting the control register (HCON); 4. Control the interrupt generation of the HDLC channel by setting the interrupt control register (HINT); 5. Set the station address register (HSAR0-HSAR3) and the station address mask register (HMASK) to complete the address comparison function of the receiving operation; 6. Establish the DMA mode of sending and receiving BUFFER descriptor linked list structure, and initialize the DMA send BUFFER descriptor pointer register (HDMATxPTR) and DMA receive BUFFER descriptor pointer register (HDMARxPTR); 7. Enable the sending and receiving functions of the HDLC channel.

3.1.1: HDLC channel reset

The HDLC channel reset can be done by setting the first 4 bits of the control register (HCON), please refer to the 4510 data sheet.

3.1.2: HDLC channel working mode configuration

Different bits in the operating mode register ( HMODE) define different operating modes. Here are some of the more commonly used mode settings. For details and configuration methods, please refer to the 4510 data sheet.

1. Data encoding method selection: Select from the five supported encoding methods.

2. Baud rate clock source selection: If you use the internal baud rate generator of 4510, you need to select the clock source for it and configure the baud rate generation counter (HBRGTC) according to different clock sources to generate the required clock signal.

3. DPLL clock source selection: If you use DPLL, you need to select the clock source to be tracked.

4. Transmit clock selection: The HDLC channel of 4510 supports multiple transmit clock sources, which can be selected by setting the corresponding bits in the mode register of the HDLC channel.

5. Receive clock selection: The HDLC channel of 4510 supports multiple receive clock sources, which can be selected by setting the corresponding bits in the mode register of the HDLC channel.

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3.1.3: HDLC channel control register configuration

The control register ( HCON) controls the operation of the HDLC channel. Commonly used control options are introduced here. For detailed content and configuration methods, please refer to the 4510 data sheet.

1. Baud rate generation /DPLL enable: If the internal baud rate generator or DPLL is used, in order to make them work, it is necessary to set the corresponding bits in the control register of the HDLC channel to start working.

2. Transmitter FIFO depth setting: When using CPU mode for HDLC transceiver, you can set the transceiver FIFO depth. The FIFO depth can be set to 8 bytes/32 bytes. When using DMA mode, this setting is invalid.

3. DMA transmission stop/skip mode setting: When using DMA transmission, if the currently used transmission BUFFER descriptor does not belong to DMA, you can stop DMA transmission according to this setting, or jump to the next descriptor in the transmission BUFFER descriptor chain list.

4. DMA reception stop/skip mode setting: When using DMA reception, if the currently used receive BUFFER descriptor does not belong to DMA, you can stop DMA reception according to this setting, or jump to the next descriptor in the receive BUFFER descriptor list.

5. Channel idle flag mode setting: Determine which idle flag (all 1s or 0X7E) is sent when the channel is idle .

6. Flag sending mode setting: determine the frame separation method (single FLAG or double FLAG mode).

7. Transmit and receive CRC check setting: Determine whether to perform CRC check during HDLC transmission and reception.

8. HDLC loopback setting: used for HDLC loopback test. The HDLC loopback should be turned on during normal operation.

3.1.4: HDLC channel interrupt control register (HINT) configuration

The interrupt control register ( HINT) controls the generation of HDLC transmission and reception interrupts. There are 24 interrupt generation conditions in total. Here are some interrupt generation conditions used in programming when DMA mode is transmitted and received. For details, please refer to the 4510 data manual.

For HDLC channel send interrupt:

1. Transmit FIFO undershoot: This condition ( TxUIE) occurs when the transmit FIFO undershoots. At this time, DMA transmission is automatically disabled, so the transmit interrupt handler must first clear the corresponding bit in the HDLC status register (HSTAT), and then enable DMA transmission before the next transmission.

2. DMA transmit Abort: This condition ( DTxABTIE) is generated when DMA transmit is abandoned, and the corresponding bit in the HDLC status register (HSTAT) must be cleared in the transmit interrupt handler.

3. DMA transmission completed: This condition ( DTxFDIE) is generated when DMA completes sending a frame. The corresponding bit in the HDLC status register (HSTAT) must be cleared in the transmit interrupt handler.

4. DMA transmit BUFFER descriptor pointer is empty: This condition ( DTxNLIE) is generated when the pointer to the next descriptor in the current DMA transmit BUFFER descriptor is empty. The corresponding bit in the HDLC status register (HSTAT) must be cleared in the transmit interrupt handler. And the transmit BUFFER descriptor linked list is reinitialized.

5. DMA transmit BUFFER descriptor does not belong to DMA: This condition ( DTxNOIE) occurs when the current DMA transmit BUFFER descriptor does not belong to DMA. The corresponding bit in the HDLC status register (HSTAT) must be cleared in the transmit interrupt handler.

For HDLC channel receive interrupt:

1. Receive Abort: This condition ( RxABTIE) is generated when an Abort frame is received, and the corresponding bit in the HDLC status register (HSTAT) must be cleared in the receive interrupt handler.

2. DMA reception completed: This condition ( DRxFDIE) occurs when DMA receives a complete frame, and the corresponding bit in the HDLC status register (HSTAT) must be cleared in the receive interrupt handler.

3. DMA receive BUFFER descriptor pointer is empty: This condition ( DRxNLIE) is generated when the pointer to the next descriptor in the current DMA receive BUFFER descriptor is empty. The corresponding bit in the HDLC status register (HSTAT) must be cleared in the receive interrupt handler and the receive BUFFER descriptor linked list must be reinitialized.

4. DMA receive BUFFER descriptor does not belong to DMA: This condition ( DRxNOIE) occurs when the current DMA receive BUFFER descriptor does not belong to DMA. At this time, DMA reception is automatically disabled. Therefore, the corresponding bit in the HDLC status register (HSTAT) must be cleared in the receive interrupt handler, and the corresponding error processing must be performed to avoid this error from happening again, and then the DMA receive function is enabled, otherwise data cannot be received.

3.1.5: Initialization of the station address registers (HSAR0-HSAR3) and station address mask register (HMASK)

4510 uses the site address stored in the 4 site address registers (HSAR0-HSAR3) in conjunction with the site address mask register (HMASK) to complete the address comparison function during the receiving process. If the address of an HDLC data frame does not match, the frame will be simply discarded without any processing. For specific settings, please refer to the 4510 data manual.

3.1.6: DMA transmit and receive BUFFER descriptor list structure establishment and pointer register initialization

The 4510 HDLC channel uses the BUFFER descriptor data structure to complete DMA operations, receiving and sending BUFFER

The descriptor and the descriptor linked list structure are shown in Figures 2, 3, and 4 respectively . In our application, a bidirectional circular linked list structure is established instead of a unidirectional circular linked list structure. The difference between the bidirectional circular linked list structure and the unidirectional circular linked list structure is that each element in the linked list has an additional pointer to the previous element. In this way, when performing linked list operations in the software, it is not necessary to traverse the entire linked list every time, which improves the processing speed.

After the linked list structure is established, the transmit and receive descriptor pointer registers need to be initialized. For the transmit BUFFER descriptor pointer register (HDMATxPTR), the head node address of the transmit BUFFER descriptor linked list structure is written into it. After that, each time a DMA transmit operation is completed, 4510 will automatically update the address therein to point to the next transmit BUFFER descriptor; for the receive BUFFER descriptor pointer register (HDMARxPTR), the head node address of the receive BUFFER descriptor linked list structure is written into it. After that, each time a DMA receive operation is completed, 4510 will automatically update the address therein to point to the next receive BUFFER descriptor.

3.1.7: Enable the HDLC channel's transmit and receive functions

After all the initialization work is done, you can enable the HDLC channel's transceiver function. There are two situations at this time:

1: If you use DMA to send and receive, you need to enable the four bits TxEN, RxEN, DTxEN, and DRxEN in the HDLC channel control register (HCON). However, when sending, you usually need to turn on the send enable only after there is data.

2. If you use the CPU mode to send and receive, you need to enable the TxEN and RxEN bits in the HDLC channel control register (HCON), and the DTxEN and DRxEN bits must not be turned on.

3.2: HDLC channel data transmission and interrupt processing process

3.2.1: HDLC channel data transmission process

The data transmission process of the HDLC channel in DMA mode can be divided into the following steps:

1. Read the transmit frame descriptor pointer register HDMATxPTR to obtain the address of the current transmit frame descriptor, and then obtain the content of the entire transmit frame descriptor.

2. Get the starting address of the frame data BUFFER in the transmit frame descriptor .

3. Copy the prepared HDLC frame to BUFFER.

4. Set the corresponding control bits in the current frame descriptor.

5. Set the OWERSHIP bit of the transmit frame descriptor to DMA ownership.

6. Enable DMA transmission of HDLC.

After completing the above steps, the DMA mechanism of the HDLC channel will automatically copy the data in the BUFFER to the HDLC channel

After a frame is sent, the 4510 automatically sets the OWERSHIP bit of the used transmit BUFFER descriptor to CPU ownership, and updates the content in the frame descriptor pointer register HDMATxPTR to the next unused transmit BUFFER descriptor address.

3.2.2: HDLC channel data transmission interrupt processing process

When a frame of data is sent through DMA, or an abnormal situation that may cause an interrupt occurs during the sending process, the software will enter the interrupt processing program. The interrupt control register setting has been explained in the interruption situation that causes the interrupt. In our programming, the HDLC channel sending interrupt processing process mainly completes the following functions:

1. After entering the interrupt, first clear the corresponding flag bit in the 4510 interrupt indication register INTPEND.

2. If the DMA transmission is successful, the data frame transmission success status count is performed and the corresponding status bit in the HDLC channel status register HSTAT is cleared.

3. If an exception occurs during transmission, the corresponding exception status count is completed and the corresponding bit in the HDLC channel status register HSTAT is cleared. There are two exceptions that will affect subsequent DMA operations: one: Transmit undershoot exception (TxU). When this exception occurs, the processor will automatically disable the DMA transmission function, so the DMA transmission function must be re-enabled for the next transmission; the other: The next transmission frame descriptor pointer is empty exception (DTxNL). When this exception occurs, it indicates that an error has occurred in the established DMA transmission BUFFER descriptor linked list structure, so the DMA transmission BUFFER descriptor linked list structure needs to be reinitialized.

4. After completing the above process, you can turn off the DMA sending function of the HDLC channel and reopen it when there is data to be sent. You can also leave it turned off.

3.3: HDLC channel data reception working principle and interrupt processing process

3.3.1: Working principle of HDLC channel data reception

The data receiving work of the HDLC channel in DMA mode is mainly completed in the HDLC channel initialization and DMA receiving interrupt processing. Here we mainly analyze the working principle of HDLC channel reception. Understanding the data receiving principle will bring great convenience to our programming. The working principle of HDLC channel reception is as follows:

1. In the channel initialization phase, we build and initialize the HDLC receive BUFFER descriptor linked list structure, and write the address of the linked list head node into the HDLC receive BUFFER descriptor pointer register HDMARxPTR. This is the premise for correctly completing DMA mode reception. The following work is automatically completed under this premise.

2. When data arrives, the DMA mechanism finds the start address of the receive BUFFER from the receive BUFFER descriptor pointed to by HDMARxPTR, and then writes the received data into the BUFFER.

3. If the reception is correct, the 4510 automatically updates the value of the HDMARxPTR register to point to the next unused receive BUFFER descriptor for the next reception. The OWERSHIP bit of the used receive BUFFER descriptor will be automatically set to CPU ownership, so in order to use this receive BUFFER descriptor again, its OWERSHIP bit must be reset to DMA ownership.

4. You can perform various custom operations on the data stored in the receiving BUFFER to achieve custom functions.

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3.3.2: HDLC channel data reception interrupt processing process

When the HDLC channel receives a frame of data in DMA mode, or an abnormal situation that may cause an interrupt occurs during the reception process, the software will enter the interrupt processing program. The situation that causes the interrupt has been explained in step 4 of the HDLC channel initialization, that is, the setting of the interrupt control register. In our programming, the HDLC channel reception interrupt processing process mainly completes the following functions:

1. After entering the interrupt, first clear the corresponding flag bit in the 4510 interrupt indication register INTPEND.

2. If DMA receives correctly, it counts the successful reception status of the data frame and clears the corresponding status bit in the HDLC channel status register HSTAT. After processing the received data frame, it resets the OWERSHIP bit of the used receive BUFFER descriptor to DMA ownership.

3. If an exception occurs during reception, the corresponding exception status count is completed and the corresponding bit in the HDLC channel status register HSTAT is cleared. Two of the exceptions will affect subsequent DMA operations: 1. The DMA receive BUFFER descriptor does not belong to the DMA (DRxNO); 2. The DMA receive BUFFER descriptor pointer is empty (DRxNL). When these two exceptions occur, it means that an error has occurred in the bidirectional ring list structure of the receive BUFFER descriptor, and the processor will automatically disable the DMA send function. Therefore, it is recommended to reconstruct the bidirectional ring list structure of the receive BUFFER descriptor and re-enable the DMA send function.

4: Precautions for using HDLC channels of S3C4510B

We have written the 4510 HDLC channel bottom-level driver and applied it to our 155M SDH equipment software. Through debugging the software, we feel that when using the 4510 HDLC channel, we need to pay attention to the following issues:

1. The big-endian/little-endian mode of the sent and received data must be consistent, otherwise the high byte and low byte of the received data will be reversed with the sent data.

2. When using DMA mode to send and receive data, after entering the interrupt in normal state, when reading the contents of the transmit BUFFER descriptor pointer register (HDMATxPTR) or the receive BUFFER descriptor pointer register (HDMARxPTR), they all point to the next unused BUFFER descriptor. Therefore, when you want to process the received data or initialize the used transmit BUFFER descriptor, you need to point back to them.

3. When using DMA mode, the OWERSHIP bit of the send and receive BUFFER descriptors must be owned by DMA when used. Because sending is active, after putting the data into the BUFFER descriptor, you can set the OWERSHIP bit and then start DMA sending; while receiving is passive, so before the data arrives, the BUFFER descriptor to be used must be owned by DMA, which is why the OWERSHIP bit of the receive BUFFER descriptor needs to be reset every time a receive interrupt is entered.

4. When the clock information of the transmitter cannot be transmitted to the receiver, it is best to use DPLL or send a preamble so that the receiver can recover the clock information of the transmitter.

5. When using an external clock source to send or receive data, pay attention to the coordination of the data sampling point and the external clock source. A chip in our device provides the clock for the HDLC channel of 4510. It sends on the rising edge of the clock and receives on the falling edge. The default mode of the HDLC channel of 4510 is to send on the falling edge of the clock and receive on the rising edge. When we send and receive data in this mode, there is a serious problem of data instability. When it is changed to sending on the rising edge and receiving on the falling edge, it is completely normal. Therefore, the coordination of the data sampling point is very important.

6. The HDLC channel of 4510 can also use interrupt mode for transmission and reception. Due to time constraints and limited capabilities, our program did not implement it. Those who are interested can refer to the 4510 data manual to implement interrupt mode transmission and reception.

5: Summary

KS4510B is a cost-effective ARM processor with rich functions and simple programming. It can be used with several embedded real-time operating systems, such as pSOS, NUCLEUS, etc. In our 155M SDH transmission equipment, 4510B and NUCLEUS operating system are used to complete the underlying control software. After debugging, the software has stable performance. The HDLC channel completes the transmission and forwarding of the private network management protocol on the SDH ring network, realizing the remote management function.

As the performance requirements of various electronic and communication products are increasing, various 32-bit microprocessors based on the advanced ARM architecture will be more and more widely used. Therefore, mastering the use and programming methods of ARM processors will definitely help you get twice the result with half the effort at work and obtain good results and benefits.