Application Design of AVR Microcontroller and Serial Clock Device DS3231

2 Structure and working principle of DS3231

The DS3231 is a low-cost, high-precision I2C real-time clock (RTC) device with an integrated temperature-compensated crystal oscillator (TCXO). The device includes a battery input to maintain accurate timekeeping when the main power supply is disconnected. The integrated crystal oscillator improves the long-term accuracy of the device. The registers of the DS3231 can store information such as seconds, minutes, hours, day of the week, date, month, year, and alarm settings. The end of the month date is automatically adjusted for months with less than 31 days, including leap year compensation. The clock operates in 24-hour format or 12-hour format with AM/PM indication. The DS3231 provides two programmable calendar alarms and one programmable square wave output. Addresses and data are transmitted via the I2C bidirectional serial bus.

2.1 Composition and working principle of DS3231

As shown in Figure 1, the main components of the DS3231 are 8 modules, divided into 4 functional groups: TCXO, power control, push button reset and RTC.

2.1.1 32 kHz TCXO

The TCXO includes a temperature sensor, an oscillator, and control logic. The controller reads the on-chip temperature sensor output and uses a table lookup to determine the required capacitance, plus the aging correction from the AGE register. It then sets the capacitor selection register. New values, including changes to the AGE register, are loaded only when the temperature changes or a user-initiated temperature conversion is completed. The temperature value is read when VCC is first powered on and then every 64 seconds.

2.1.2 Power Control

The power control function is provided by a temperature-compensated voltage reference (VPF) and a comparator circuit that monitors the VCC level. The DS3231 is powered by VCC when VCC is above VPF, by VCC when VCC is below VPF but above VBAT, and by VBAT when VCC is below VPF and below VBAT. To protect the battery, the oscillator does not start when VBAT is first applied to the device, unless VCC is loaded or a valid I2C address is written to the device. Typical oscillator startup time is less than 1 s. Approximately 2 s after VCC is applied or a valid I2C address is written, the device measures the temperature and calibrates the oscillator using the calculated correction value. Once the oscillator is running, it will remain operational as long as the power supply (VCC or VBAT) is valid. The device takes a temperature measurement and calibrates the oscillator frequency every 64 s.

2.1.3 Push button reset

The DS3231 has a push button switch function connected to the RST output pin. If the DS3231 is not in a reset cycle, it will continuously monitor the falling edge of the RST signal. If an edge transition is detected, the DS3231 completes the switch debounce by pulling RST low. After the internal timer expires, the DS3231 continues to monitor the RST signal. If the signal remains low, the DS3231 continues to monitor the signal line to detect a rising edge. Once the button release is detected, the DS3231 forces RST to a low level and holds tRST. RST can also be used to indicate a power failure alarm condition. When VCC is below VPF, an internal power failure alarm signal is generated and the RST pin is forced low. When VCC returns to a level above VPF. RST remains low for approximately 250 ms (tREC) to allow the power supply to stabilize. If the oscillator is not working when VCC is loaded, tREC will be skipped and RST will immediately go high.

2.1.4 Clock and Calendar RTC

The clock and calendar information can be obtained by reading the appropriate register byte. The clock and calendar data are set or initialized by writing the appropriate register byte. The contents of the clock and calendar registers are in binary coded decimal (BCD) format. The DS3231 operates in 12-hour or 24-hour mode. Bit 6 of the hour register is defined as the 12- or 24-hour mode select bit. When this bit is high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM indicator bit, which is PM when logic high.

2.1.5 Alarm Clock

The DS3231 contains two time/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (via the alarm enable and INTCN bits of the control register) to trigger the INT/SQW output on an alarm match condition. Bit 7 of each time/date alarm register is the mask bit. When the mask bit of each alarm is logic 0, the alarm will only sound when the value in the time register matches the corresponding value stored in the time/date alarm register. The alarm can also be programmed to repeat every second, minute, hour, day of the week, or date. When the RTC register value matches the set value of the alarm register, the corresponding alarm flag bit A1F or A2F is set to logic 1. If the corresponding alarm interrupt enable bit A1IE or A2IE is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition will trigger the INT/SQW signal. The RTC checks for a match every second when the time and date registers are updated.

2.2 DS3231 internal registers and functions

The DS3231 register addresses are 00h to 12h, which are used to store seconds, minutes, hours, days of the week, date, and alarm setting information. During multi-byte access, if the address reaches the end of the RAM space at 12h, wraparound will occur, and the address will be located at the beginning, i.e., unit 00h. The time and calendar information of the DS3231 is set and initialized by reading the corresponding registers. The auxiliary (user) buffer is used to prevent errors that may occur when the internal registers are updated. When reading the time and calendar registers, the user buffer is synchronized with the internal registers at any START condition or when the register pointer returns to zero. The time information is read from these auxiliary registers, and the clock continues to run. This avoids re-reading the registers when the main register is updated during the read operation. Taking the control register (address 0EH) as an example, the real-time clock, alarm clock, and square wave output can be controlled. The definitions of each bit are shown in Table 1.

BIT7: Enable oscillator (EOEC). When set to logic 0, the oscillator starts. If set to logic 1, the oscillator stops when the DS3231 power supply switches to VBAT. This bit is cleared (logic 0) when the DS3231 is powered by VCC. When the DS3231 is powered by VCC, the oscillator remains operational regardless of the state of the EOSC bit. [page]

BIT6: Battery Backup Square Wave Enable (BBSOW). When set to Logic 1 and the DS3231 is powered from the VBAT pin, this bit enables the square wave output when VCC is not loaded. When BB-SQW is set to Logic 0, the INT/SQW pin becomes high impedance if VCC drops below the power-fail threshold. This bit is cleared (Logic 0) when power is first applied.

BIT5: Convert Temperature (CONV). When this bit is set to 1, it forces the temperature sensor to convert the temperature to digital and executes the TCXO algorithm to update the capacitor array of the oscillator. It is valid only during idle time. When status bit BSY = 1, the conversion temperature bit is disabled. The user should check the status bit BSY before forcing the controller to start a new TCXO operation. User-initiated temperature conversions do not affect the internal 64 s update cycle. User-initiated temperature conversions do not affect the BSY bit for approximately 2 ms. The CONV bit remains 1 from the time it is written until the conversion is completed, after which both CONV and BSY become 0. The CONV bit should be used when monitoring the status of user-initiated conversions.

Bits BIT4 and BIT3: Frequency selection (RS2 and RS1). When powered on for the first time, BIT4 and BIT3 are set to logic 1. They are used to control the frequency of the square wave output when the square wave is enabled. The relationship between the logic values ​​of RS1 and RS2 and the square wave output frequency is listed in Table 2.

BIT2: Interrupt Control (INTCN). This bit controls the INT/SQW signal. When INTCN is set to 0, the INT/SQW pin outputs a square wave. When INTCN is set to 1, if the timer register matches any of the alarm registers, the INT/SQW signal is triggered (if the alarm is also enabled). When a match occurs, the corresponding alarm flag is always set, regardless of the state of the INTCN bit. When power is first applied, the INTCN bit is set to logic 1.

BIT1: Alarm 2 Interrupt Enable (A2IE). When this bit is logic 1, it allows the Alarm 2 Flag (A2F) in the Status Register to trigger the INT/SQW signal (when INTCN = 1). When the A2IE bit is 0 or INTCN is set to 0, the A2F bit does not start the interrupt signal. When the power is first turned on, the A2IE bit is cleared (logic 0).

BIT0: Alarm 1 Interrupt Enable (A1IE). When this bit is logic 1, it allows the Alarm 1 Flag (A1F) in the Status Register to trigger the INT/SQW signal (when INTCN = 1). When the A1IE bit is 0 or INTCN is set to 0, the A1F bit does not start the INT/SQW signal. When power is first applied, the A1IE bit is cleared (logic 0).

2.3 DS3231 data exchange and format

The DS3231 is a slave device on the I2C bus. It is accessed by executing a START command and after verifying the device address. The registers can then be accessed until a STOP command is executed.

All address packets transmitted on the I2C bus are 9 bits long, including 7 address bits, 1 R/W control bit and 1 ACK bit. If R/W is 1, a read operation is performed; if R/W is 0, a write operation is performed. After the slave is addressed, it must respond by pulling down SDA in the 9th SCL (ACK) cycle. If the slave is busy or unable to respond to the master, SDA should be kept high during the ACK cycle. The master then issues a STOP state or a REP START state to restart transmission. The address packet includes the slave address and the READ or WRITE bit called SLA+R or SLA+W. The MSB of the address byte is sent first. All addresses of 1111xxxx are reserved. For future use.

All data packets transmitted on the I2C bus are 9 bits long, which includes 8 data bits and 1 acknowledge bit. During data transmission, the host generates the clock and START and STOP states, and the receiver responds to reception. The acknowledgement is achieved by ACK pulling SDA low in the 9th SCL cycle. If the receiver pulls SDA high, a NACK signal is sent. If the receiver cannot receive more data for some reason, it should send a NACK signal after the last data byte to tell the transmitter to stop sending and send the MSB of the data first.

DS3231 exchanges data with the outside world through the bidirectional data line SDA and the clock line SCL. From the timing relationship, we can see that DS3231 has two operation modes:

(1) Write operation: Write the data on the SDA data line into N bytes of data in sequence according to the first address (Word Address) specified by the RAM. The master device first transmits the address byte of the slave device, followed by a series of data bytes. The slave device returns an ACK bit after receiving each byte. The format is shown in Figure 2.

(2) Read operation: Read N bytes of data in sequence according to the first address specified by the RAM. The master device first transmits the slave device address. The slave device returns an acknowledge bit. This is followed by a series of data bytes transmitted by the slave device. The master device returns an acknowledge bit after receiving all bytes except the last byte. After receiving the last byte, it returns a "non-acknowledge bit" NACK. Its format is shown in Figure 3.

In the above read and write operation signals: S is the start signal (START), 1101 000 is the port address of DS1307, A is the response signal ACK, A is the non-response signal NACK, and P is the stop signal (STOP). The master device generates all serial clocks and START and STOP conditions, and stops it by transmitting STOP and resending START conditions.

3 Hardware interface between DS3231 and AVR microcontroller

The ATmega series microcontrollers have an integrated 2-wire serial interface module. Atmel calls it the TWI interface. In fact, TWI is the same as Philips' I2C bus. The TWI interface implemented by AVR hardware is byte-oriented and interrupt-based. It has better real-time performance and code efficiency than the software-simulated I2C bus. The pin input part also has a glitch suppression unit to remove high-frequency interference. Figure 4 is the schematic diagram of the hardware interface circuit between DS3231 and AVR microcontroller ATmega8.

4 Software interface between DS3231 and AVR microcontroller

In software design, the AVR microcontroller ATMega8 and the real-time clock device DS3231 must be initialized first. Give the DS3231 an accurate date and time. Regardless of the master mode or the controlled mode, the TWEN bit of the TWI control register TWCR should be set to 1 to enable the TWI module. After the TWEN bit is set, the I/O pins PC5 and PC4 are converted to SCL and SDA. The operation of the TWI control register TWCR can generate START and STOP signals on the bus. From START to STOP, it is considered to be the behavior of the master mode. Set the first bit TWGCE of the TWI address register TWAR to valid, and set the TWEA (response enable) bit of the TWI control register TWCR to 1. The TWI module can respond to its addressing on the bus and set the status word. The operations on the TWI module are all register read and write operations. Avr-libc does not provide a special API. The standard I/O based on US-ART can be used to implement the operations of reading and writing calendars and clocks on DS3231. The following program is part of the code for the interface between DS3231 and AVR microcontroller: [page]

5 Conclusion

A calendar clock system is designed by using the real-time clock device DS3231 and the AVR microcontroller ATmega8. The system is small in size and highly versatile. The DS3231 has an integrated temperature compensated crystal oscillator (TCXO), which is accurate in timing and does not produce errors with seasonal changes. The system is suitable for smart display screens and real-time measurement and control systems.