Mixed Logic Level Interface Technology

Driven by the application requirements of portable devices with low power consumption and small size (cellular phones, PDAs, laptops, digital cameras, etc.), more and more semiconductor devices adopt low-voltage design technology. Many semiconductor device manufacturers have launched a series of ultra-low power integrated circuits such as 3.3V and 2.5V. This has enabled many low-voltage logic standards to be widely used. In the design process of new generation bank terminals, educational terminals and other products, in order to reduce costs and maintain compatibility with terminal peripherals, it is also necessary to use many devices with different logic standards in the same system. Therefore, modules with different power supply voltages are inevitably present in the same system. How to solve the interface problem between different logic level signals has become a key technology faced by hardware engineers. Combined with the design of TFT color LCD network terminal, this article introduces the interface characteristics of several logic level signals in detail and discusses the interface technology between them.

1 DC/DC power conversion

Traditional linear regulators, such as the LM117 series, require the input voltage to be more than 3V higher than the output voltage, otherwise they will not work properly. At the same time, traditional linear regulators have low conversion efficiency and high heat generation, so the LM117 series can no longer meet the power design requirements of low-power and small-volume application systems. Battery-powered portable devices have higher requirements for power conversion efficiency and heat dissipation, so other solutions must be sought.

The mainboard of the TFT color LCD network terminal involves a large number of 5.0V and 3.3V logic signals, and must have two power supply modules of 5.0V and 3.3V. In order to be compatible with the external power supply of other series terminals, the LM2576 of National Semiconductor is used here to convert from 12V to 5V, and then the MIC5207 of MICREL (or LT1086 of Linear) is used to convert from 5V to 3.3V.

LM2576 is a low voltage output monolithic integrated circuit based on switching power supply technology. It has a built-in 52kHz oscillation circuit and only requires 4 peripheral devices. The power conversion efficiency is as high as 77%, the maximum output current can reach 3A, the heat generation is small, the electromagnetic radiation is small, and the reliability is high.

In response to the demand for low-voltage power supplies, many power chip companies have launched low-dropout linear regulators (LDOs). The voltage drop of this power chip can be as low as 0.2V to 1.3V, which can achieve requirements such as 5V to 3.3V/2.5V, 3.3V to 2.5V/1.8V, etc. There are many companies that produce LDOs, such as ALPHA, LT (Linear Technology), NI (National Semiconductor), TI, etc. The low-dropout linear regulator MIC5207 is particularly suitable for handheld battery-powered devices. It has an enable control pin compatible with COMS and TTL levels, which is convenient for shutting down the power supply to reduce power consumption, and its peripheral circuit is also particularly simple.

2 Electrical characteristics of various logic level signals

In the TFT color LCD network terminal system, the I/O port of the central processor Intel PXA255 is a 3.3V CMOS structure; the I/O port of the USB Host controller SL811HS is a 3.3V CMOS structure, which is compatible with TTL level; the super I/O controller W83977ATF has two I/O ports: 5.0V CMOS and 5.0V TTL. Their level characteristics are shown in Table 1. Different devices that comply with the same logic level standard may have slightly different electrical characteristics of the port. Even the same device may show different electrical characteristics in different environments. Therefore, when designing the circuit, it is necessary to analyze the specific situation.

In Table 1, VOH indicates the minimum value of the output high level; VOL indicates the maximum value of the output low level. Table 1 VIH indicates the minimum value of the input high level; VIL indicates the maximum value of the input low level. Table 1 lists the common electrical characteristics of the devices, and some integrated circuits are slightly different.

Bank terminals require more than 8 external serial port devices, so solving the RS-232C serial port and 3.3V and 5.0V logic level interface is also an important technology of the TFT color LCD network terminal system (some terminals of Star Computer Company have TTL level serial ports).

RS-232C standard is a communication protocol developed by EIA (Electronic Industry Association) and BELL and other companies in the United States and announced in 1969. Its full name is EIA-RS-232C. It is suitable for communication with data transmission rate of 0 to 20,000 bps. This standard clearly stipulates the relevant issues of serial communication interface, such as signal line function and electrical characteristics. Since communication equipment manufacturers all produce communication equipment compatible with RS-232C standard, it has been widely used in microcomputer communication interface as a standard.

RS-232C uses negative logic, stipulating that any voltage from +3V to +15V represents logic 0 (or valid signal), and any voltage from -3V to -15V represents logic 1 (or invalid signal).

At present, the manufacturers of TFT LCD screens mainly include LG, PHILIPS, SAMSUNG, SHARP, NEC, etc. Some of these screens have TTL level interfaces, while others have LVDS interfaces. The effective distance of using TTL level interfaces is only 50cm. If it is 3.3V level, the transmission distance is even shorter. In terminal applications, the display screen is generally integrated with the host, but there are also cases where the display screen is far away from the host, so here is a brief introduction to LVDS signals. At present, LVDS technology has its limitations in transmission distance, and is generally used below 20m.

LVDS (Low Voltage Differential Signaling) is a small amplitude differential signaling technology that uses very low amplitude signals (about 350mV) to transmit data through a pair of differential PCB traces or balanced cables. LVDS is defined in two standards: IEEE P1596.3 (approved in March 1996), which is mainly for SCI (Scalable Coherent Interface); ANSI/EIA/EIA-644 (approved in November 1995), which mainly defines the electrical characteristics of LVDS and recommends a maximum rate of 655Mbps and a theoretical limit rate of 1.823Gbps on a lossless medium. In both standards, characteristics are specified that are independent of the physical medium, meaning that as long as the medium transmits the signal to the receiver within the specified noise margin and skew tolerance range, the interface will function properly.

Figure 1 is a schematic diagram of the LVDS principle. Its driver consists of a constant current source (usually 3.5mA) driving a pair of differential signal lines. There is a high DC input impedance at the receiving end (almost no current consumption), so almost all of the drive current will flow through the 100Ω terminal resistor to generate a voltage of about 350mV at the receiver input. When the drive state is reversed, the direction of the current flowing through the resistor changes, thus generating a valid "0" or "1" logic state at the receiving end.

The constant current source mode low swing output of LVDS technology means that LVDS has a very high transmission speed, can better suppress common mode signals, the parallel differential signal reduces the surrounding electromagnetic interference, and the CMOS process ensures low static power consumption. In addition, because it is a low swing differential signal technology, its drive and reception do not depend on the power supply voltage. Therefore, LVDS can be easily applied to low voltage systems, such as 3.3V or even 2.5V, to maintain the same signal level and performance. LVDS is also easy to match the terminal. Whether its transmission medium is a cable or a PCB trace, it must be matched with the terminal to reduce unwanted electromagnetic radiation and provide the best signal quality. Usually, a 100Ω terminal resistor as close to the receiving input as possible across the differential line can provide a good match. [page]

3.3V and 5.0V level signal conversion

In a mixed voltage system, there are several problems when logic devices with different supply voltages interface with each other:

First, the maximum voltage limit allowed on the input and output pins. Devices usually have a limit on the voltage applied to the input or output pins. These pins are connected to Vcc by diodes or discrete components. If the input voltage is too high, the current will flow to the power supply through the diode or discrete component. For example, if a 5V signal is added to the input of a 3.3V device, the 5V power supply will charge the 3.3V power supply. The continuous current will damage the diode and other circuit components.

Second, there is the problem of the cross-current between the two power supplies. When in the waiting or power-off mode, the 3.3V power supply drops to 0V, and a large current will flow to the ground, which causes the high voltage on the bus to be pulled down to the ground. These situations will cause data loss and component damage. It must be noted that no matter in the 3.3V working state or in the 0V waiting state, current is not allowed to flow to Vcc.

Third, the interface input conversion threshold problem. There are many situations in the interface between 5V devices and 3.3V devices, and there are also different situations in the level conversion between TTL and CMOS. The driver must meet the input conversion level of the receiver and have enough tolerance to ensure that the circuit components are not damaged.

Based on the above situation, 5V devices and 3.3V devices cannot be directly interfaced. Some semiconductor device manufacturers have launched 3.3V devices with 5V input tolerance, and the input end of this device has an ESD protection circuit. In fact, all input ends of digital circuits have an ESD protection circuit. The traditional CMOS circuit limits the negative high voltage through the grounding diode, and the positive high voltage is clamped by the diode. The disadvantage of this circuit is that the maximum input voltage is limited to 3.3V + 0.5V (diode voltage drop) (otherwise the current will flow to the 3.3V power supply). The output voltage of most 5V systems can reach more than 3.6V, so the 3.3V device using this circuit structure cannot be directly interfaced with the output end of the 5V device. If a MOS field effect tube equivalent to a fast Zener diode is used instead of the above clamping diode to achieve high voltage limiting, and the diode connected to Vcc (3.3V) is removed, the maximum input voltage is not limited by Vcc (3.3V). Typically, the breakdown voltage of this circuit is between 7V and 10V. Therefore, the input end of this improved 3.3V system with ESD protection circuit can withstand an input voltage of 5V. In order to prevent the problem of current backflow at the output end of the 3.3V device, a protection circuit is also required at the output end. When the voltage applied to the output end is higher than Vcc (3.3V), the comparator of the protection circuit will disconnect the current backflow path, so that it can be connected to the 5V device in the three-state mode.

Analyzing the electrical characteristics of various logic level signals (see Table 1), it is found that there are the following five interface situations:

First, when a TTL device with the same supply voltage drives a CMOS device, the output high level of the TTL device may not reach the minimum value of the input high level of the CMOS device. The VOH of a 3.3V TTL device is 2.4V, and the VIH of a 3.3V CMOS device is 0.8VCC (3.3V×0.8=2.64V); the VOH of a 5.0V TTL device is 2.4V, and the VIH of a 5.0V CMOS device is 0.7VCC (3.5V). In order to transmit data reliably, the output end of the TTL device can be pulled up. Some devices manufactured by CMOS process are compatible with TTL level, so they can be directly interfaced with TTL devices with the same supply voltage without pull-up.

Second, CMOS devices with the same supply voltage drive TTL devices, the levels are matched, and data can be transmitted reliably.

Third, when TTL devices with different supply voltages drive CMOS devices, the output high level of the TTL device may not reach the minimum value of the input high level of the CMOS device. The VOH of the 3.3V TTL device is 2.4V, and the VIH of the 5.0V CMOS device is 0.7VCC (3.5V), so the levels do not match; the VOH of the 5.0V TTL device is 2.4V, and the VIH of the 3.3V CMOS device is 0.8VCC (2.64V), so the output end of the 5.0V TTL device can be pulled up to achieve the purpose of level matching.

Fourth, when CMOS devices with different supply voltages drive TTL devices, the levels are matched and data can be transmitted reliably if the input end has a 5V tolerance.

Fifth, TTL devices with different supply voltages can be directly interfaced if the input has a 5V tolerance; CMOS devices with different supply voltages cannot be directly interfaced due to level mismatch.

From the above analysis, we can know that level signals of different logic standards cannot be directly interfaced. When only a small number of signals need level conversion, you can consider pull-up resistors or select devices with 5V input tolerance, or even consider resistor voltage division to reduce the input voltage. For a large number of signals that need level conversion, in order to reliably transmit data, a bidirectional driver powered by dual voltage (3.3V on one side and 5V on the other side) can be used to achieve level conversion. For example, the 74LVX4245 of Fairchild Semiconductor, the SN74ALVC164245 of TI
, and the SN74ALVC4245 can better solve the problem of 3.3V and 5V level conversion.

4 Conversion between 3.3V, 5.0V level signal and RS-232 level signal

In the TFT color LCD network terminal system, the Intel PXA255 microprocessor has three UART ports compatible with the 16550 standard and a 3.3V CMOS logic structure. The terminal peripherals generally comply with the RS-232C standard serial port, so it is necessary to convert the level and logic relationship between EIA-RS-232C and Intel PXA255. There are many ways to achieve this conversion, which can be achieved by using separate components or integrated circuits. At present, integrated circuit conversion devices are widely used, such as MC1488, SN75150 and other chips, which can complete the conversion from TTL level to serial port level. MC1489 and SN75154 can realize the conversion from serial port level to TTL level. Chips such as MAX232/MAX232A, MAX3221/MAX3223 can complete the bidirectional conversion between multiple 3V~5V levels and serial port levels. In the TFT color LCD network terminal system, there are up to 8 serial ports. Considering the price and circuit complexity, HIN232 from Intelsil Company is selected. The supply voltage of HIN232 is 5.0V, and the logic level of the output pin of its receiving module and the input pin of its sending module are compatible with TTL/CMOS.

5. Conversion between 3.3V level signal and LVDS signal

The LCD control module of Intel PXA255 microprocessor provides 16-bit display data, horizontal and vertical synchronization signals, pixel clock, and output enable signal. In TFT display mode, 5 bits are for red, 6 bits for green, and 5 bits for blue. These signals are all 3.3V CMOS level. The DS90C385 transmitter launched by National Semiconductor is specially used to convert LVTTTL and LVCMOS signals into LVDS data streams. When selecting the conversion chip, it is important to pay attention to whether the conversion rate meets the system requirements.

In the design of future digital logic systems, we will often encounter mixed logic level interface problems. As long as we have a deep understanding of the electrical characteristics of various logic levels and pay attention to some specific issues, such as conversion rate, we can design the correct interface circuit to ensure reliable data transmission.