Features and Applications of USB2.0 Controller CY7C68013

1 Main features of USB2.0

Version 2.0 of the USB protocol was released in April 2000. It supports the following three speed modes:

Low speed mode: 1.5Mb/s;

Full speed mode: 12Mb/s

High speed mode: 480Mb/s

The USB2.0 protocol supports all existing USB devices . It can plug a USB1.1 device into a USB1.1 PC port and is electrically compatible with USB1.1 cables. 1.1 Data Packet

The types of data packets transmitted by USB are defined by specific codes called Packet Ids (PIDs). There are four types of PIDs in USB packets, as listed in Table 1.

Table 1 USB2.0 data packet types

Note: Bold words indicate the PID types added by USB2.0.

In full-speed mode, each OUT transmission sends an OUT data packet, regardless of whether the peripheral is in a "busy" state and cannot receive data. To address this waste of bandwidth, a new PID type "PING" is recommended in high-speed mode. The host first sends a shorter "PING" token to the OUT endpoint to access whether the current peripheral has data diploma space to store the OUT data packet. Only when the external device responds with "ACK" does the host send a longer OUT data packet.

The SETUP card is only used for control transmission. It is the first 8 bytes in the data packet. Through these 8 bytes, the peripheral decodes the device request of the host.

The SOF token represents the start of a USB frame.

ACK (Acknowledge) indicates success and data is received correctly.

NAK (Negavite Acknowledge) means busy, it has to be sent. This is not an error, but the USB peripheral's failure to respond indicates an error.

STALL indicates an unknown error. The peripheral fails to understand the device request sent by the host. It may be an error on the peripheral side or a resource that the host accesses and exists. The USB protocol provides a way to recover from the stall state.

For details on other PIDs, please refer to reference [1].

1.2 Frame Structure

The USB host sends a SOF packet (Start of Frame) to all USB devices every millisecond to provide a time reference. SOF includes an 11-bit self-increasing frame number. FX2 can read this frame number in the range of [0 to 2047] from the register at any time.

In high-speed mode (480Mb/s), each 1ms long frame is divided into 8 125μs long microframes. Each microframe also starts with a SOF packet. The frame number is still incremented once every millisecond, so these 8 microframes have the same frame number. In order to distinguish each microframe, FX2 provides a read-only microframe counter, and FX2 can generate an interrupt request when receiving a SOF packet, that is, 1ms/time in full-speed mode and 125μs / time in high-speed mode.

1.3 Transmission Type

In order to adapt to the high-speed data transmission of 480 Mb/s, the USB.0 protocol has expanded the length of data packets of various transmission types. The comparison with USB1.1 is listed in Table 2. [page]

Table 2 Comparison of USB2.0 and USB1.1 data packet lengths

1.4 High-speed mode and full-speed mode detection

The USB2.0 specification requires that high-speed devices must be able to enumerate in full-speed mode. Each high-speed device begins the enumeration process in full-speed mode. After reaching a "Chirp" agreement with the host, the device switches to high-speed operation mode. For details, see Chapter 7 of reference [1]. FX2 can automatically detect high-speed hosts and switch to high-speed mode.

1.5 Transmission Performance Analysis

Taking USB hard disk as an example, the high-speed transmission performance of USB2.0 is analyzed. Figure 1 shows the bandwidth analysis of the USB2.0 and hard disk interface.

An ATA100 hard drive with a 7200 rpm and 2MB cache has an interface data transfer rate of up to 100MB/s, but the sustainable effective transfer rate is only 39MB/s.

USB2.0 can transmit up to 13 block transfer packets in each upper microframe, and the length of each microframe is fixed at 125 μs , so its maximum transmission rate is: 512×13×8×1000=53MB/s.

2 Main features of EX-USB FX2

2.1 Chip Structure

The EZ-USB FX2 chip includes an 8051 processor, a serial interface engine (SIE), a USB transceiver, 8.5KB on-chip RAM, 4KB FIFO memory, and a general programmable interface (GPIF), as shown in Figure 2. FX2 is a fully integrated solution that takes up less board space and shortens development time.

EZ-USB FX2 has a unique architecture, including an intelligent serial interface engine (SIE). It performs all basic USB functions, freeing the embedded MCU to implement dedicated functions and ensuring its continuous high-performance transmission rate. FX2 also includes 2 general programmable interfaces (GPIF), allowing it to connect to any ASIC or DSP "without glue", and it also supports all common bus standards, including ATA, UTOPIA, EPP and PCMCIA. EZ-USB FX2 is fully applicable to USB2.0 and backward compatible with USB1.1.

FX2 has three package types: 56-pin SOPP, 100-pin TQFF (Thin Quad Flat Package), and 128-pin TQFP. The difference in the number of pins is the number of input and output pins, which is different for different application requirements.

2.2 Structural characteristics

Most USB1.1 devices require the microcontroller to participate in the data transfer from the endpoint FIFOs to the application environment, as shown in Figure 3. Obviously, the operating frequency of the microcontroller itself limits the further improvement of bandwidth to a considerable extent. Although this limitation is not obvious in the full-speed mode of 12Mb/s, when the speed is increased to 480Mb/s, the microcontroller will inevitably become the bandwidth bottleneck of the entire system under strict cost control.

EZ-USB FX2 provides a unique architecture that allows the USB interface and the application environment to directly share FIFOs, while the microcontroller does not participate in data transmission but allows access to these shared FIFOs in the form of FIFOs or RAM, as shown in Figure 4. This processing architecture, called "Quantum FIFO", better solves the bandwidth problem of USB high-speed mode.

Specifically, as shown in Figure 5, the USB performs an OUT transfer and sets the EP2 endpoint to a 512-byte quad FIFO (as described in Section 2.3). Neither the USB nor the external interface knows that there are quad FIFOs. It seems that as long as one FIFO is "half full" on the USB side, data can continue to be sent. When the FIFO being operated is written "full", FX2 automatically switches it to the external interface side, excluding the waiting read; and transfers the next "empty" FIFO in the USB interface queue to the USB interface for it to continue writing data. The external interface side is similar. As long as one FIFO is "half full", data can continue to be read. When the currently operated FIFO is read "empty", FX2 automatically switches it to the USB interface side, excluding the waiting write; and transfers the next "full" FIFO in the external interface queue to the external interface for it to continue reading data. [page]

2.3 Endpoint Cache

The USB protocol defines endpoints as data receivers and transmitters. The host sends a 4-bit address and a 1-bit direction to select an endpoint, so USB can have up to 32 endpoints defined: IN0 to IN15 and OUT0 to OUT15.

FX2 defines 7 endpoints. The endpoint cache structure in high-speed mode is shown in Figure 6. EP0IN&OUT, EP1IN, and EP1OUT are 64-byte endpoint caches. EP0 is the default control transfer endpoint, which is both an IN endpoint and an OUT endpoint. EP1IN and EP1OUT support block, interrupt, and synchronous transfers. EP0, EP1IN, and EP1OUT can only be accessed by the FX2 firmware; while EP2, 4, 6, and 8 can transfer high-speed data to and from the same chip without firmware intervention.

FX2 endpoint configuration is very flexible. EP2, 4, 6 and 8 are large-capacity, high-bandwidth data transfer endpoints that can be set as either IN or OUT endpoints and can be configured in a variety of ways to accommodate bandwidth needs. In Figure 6, each column represents a configuration. The shaded box can include 2, 3, or 4 512- or 1024-byte buffers, indicating that the endpoint can be configured as double, triple, and quadruple buffers, respectively. Double buffering means that the USB can read or write one data packet, while the other data packet (in another buffer memory in the same endpoint) is available for external interface operations; triple buffering adds a third data packet memory for use by the USB and the external interface; quadruple buffering adds a fourth data packet memory. The multi-buffer structure effectively improves bandwidth, smooths bandwidth jitter, and reduces the waiting time between the two parties when the speeds of the read and write parties are similar.

3 EZ-USB FX2 interface

FX has two interface modes: Slave FIFOs and programmable interface GPIF.

Slave FIFOs mode is a slave mode, and the external controller can read and write the multi-layer buffer FIFO of FX2 like a normal FIFO. The working mode of FX2's Slave FIFOs can be set to synchronous or asynchronous; the working clock can be selected to be internally generated or externally input; other control signals can also be flexibly set to high or low effective.

The programmable interface GPIF is a host mode, which can read and write control waveforms by software programming. It can actively read and write data to almost any 8/16 bit interface controller, memory and bus, which is very flexible. 4 EZ-USB FX2 development tools

Like other controllers in the EZ-USB series, Cypress also provides a relatively complete development kit CY3681 for FX2. It includes a hardware development board with a 128-pin CY7C68013 and a corresponding control panel (Control panel), GPIF code automatic generation software (GPIFTool), and a wealth of firmware examples and a large number of help documents. It can save learning time as much as possible and speed up development.