Brief introduction to the function and principle of DEI1016 and its interface design with single chip microcomputer

1 Main functions of DEI1016

DEI1016 is a serial receiving and transmitting device produced by Device Engineering Instrumented that supports the ARINC429 aviation bus protocol. The main functions of this device are as follows:

●Serial data word length is 32 or 25 bits;

●Serial data rate is 100kbps or 12.5kbps;

●With independent receiving and transmitting circuits;

●Two independent receivers can directly interface with the ARINC429 bus;

●It has the functions of serial/parallel receiving data conversion and parallel/serial sending data conversion;

● Parity check can be performed on received data; and parity status of sent data can be set;

●Can automatically generate spaces between words;

●Using a single +5V power supply.

2 Working principle of DEI1016

The pin functions and features of DEI1016 have been introduced before, and now we will only describe the working principle of the device.

2.1 Reset and initialization of DEI1016

After the circuit is powered on, first apply a 200μs low-level pulse to the MR pin to reset DEI1016, and then write the control word to the 16-bit data bus. In this way, applying a low level to the LDCW pin can write the control word to the control word register, and then data can be received and sent.

2.2 Data transmission process of DEI1016

The data transmission timing of DEI1016 is shown in Figure 1. When sending data, first check whether the TXR pin is high. If it is high, it means that the transmission memory is empty. At this time, set the ENTX pin to low to stop sending data and write the data to be sent to the 16-bit data bus. After that, if you want to send data word 1, set LD1 to low and LD2 to high; if you want to send data word 2, set LD1 to high and LD2 to low? At this time, check whether the TXR pin is low. If it is low, it means that the transmission data has been loaded into the memory. At this time, set the ENTX pin to high to send data. The transmission memory of DEI1016 can load up to 8 32-bit word length data. DEI1016 adopts the first-in-first-out transmission order.

2.3 Data Receiving Process of DEI1016

The data receiving timing of DEI1016 is shown in Figure 2. When receiver 1 receives data, the system will set DR1 to a low level; and when receiver 2 receives data, the system will set DR2 to a low level. To make receiver 1 send word 1 of the received data to the 16-bit data bus, first set SEL to a low level, then set OE1 to a low level and set OE2 to a high level. Then set SEL to a high level, and word 2 can be sent to the 16-bit data bus. To make the data of receiver 2 be sent to the 16-bit data bus, set OE2 to a low level and OE1 to a high level.

Table 1 74LS373 function table

3 Interface Design between AT89C52 and DEI1016

When the AT89C52 (U1) 8-bit microcontroller exchanges data with the 16-bit data bus of DEI1016, the latch must be used to latch the data first. The interface circuit block diagram is shown in Figure 3. When sending data, U1 first divides the data to be sent into the lower 8 bits and the upper 8 bits and sends them out, and enters U3 and U4 for latching, and then sends the 16-bit data together to the data bus of DEI1016?U2?. U3, U4, U5, and U6 all use 74LS373 chips, and their internal parts are composed of D latches and three-state output gates. Their function table is listed in Table 1. When OE is low and G is high, the output Q and input D are in direct connection. When OE is high and G changes from high to low, the input data of D is latched by D latch. Even if the input data of D (P0 port) changes again, it will not affect the latched data. If OE is low, the system will output the previously latched data. In order to latch the lower 8-bit data, the WR of U1 and the address selection signal Y7 (decoded by decoder U7) need to control the G terminal of U3 through the NOR gate U8. In fact, only when U1 is performing a write operation, WR and Y7 are both low, and at this time, the lower 8-bit data can be temporarily latched by U3. The latching of the high 8-bit data is similar to this. When P3.4 of U1 changes from high to low, it can open the output gates of U3 and U4, so that U3 and U4 send data to the data bus of U2. When P1.3 or P1.4 of U1 changes from high to low to load 16-bit data into the transmission memory, P3.4 will change from low to high. At this time, the output of U3 and U4 is in a high impedance state, but it will not affect the data output state of U2. The transmission procedure is as follows:

mov dptr, #e000h

move a, #d11; get the lower 8 bits of word 1

movx @dptr,a; lock the lower 8 bits of word 1 into U3

mov dptr,#c000h

move a, #d1h; get the high 8 bits of word 1

movx @dptr,a; lock the upper 8 bits of word 1 into U4

clr p3.4 ; turn on the output of U3 and U4

nop

clr p1.3; word 1 data loaded into DEI1016

nop

SETBB P3.4 ; Turn off the output of U3 and U4

SET 1.3

mov dptr, #e000h

move a, #d21; get the lower 8 bits of word 2

movx @dptr,a; lock the lower 8 bits of word 2 into U3

mov dptr，#c000h[page]

move a, #d2h; get the high 8 bits of word 2

movx @dptr,a; lock the upper 8 bits of word 2 into U3

clr p3.4 ; turn on the output of U3 and U4

nop

clr p1.4; word 2 data loaded into DEI1016

nop

SET 3.4

SETPB1.4

Use U1 to receive data. DR1, DR2 and TXR should be connected to INT0 of U1 through AND gate U13. After an interrupt is generated at INT0 port, U1 performs a read operation and controls U14 and U15 through RD and Y5 to read the status of DR1, DR2 and TXR. After U2 receives data or completes sending data, it applies for an interrupt to INT0 port of U1 and determines the status of DR1, DR2 and TXR in the interrupt program. TXR is low, indicating that the transmission is completed, while DR1 or DR2 is low, indicating that the data has been received. At this time, P1.2 (SEL) can be set to low level, and P1.0 (connected to OE1 of DEI1016) or P1.1 (connected to OE2 of DEI1016) can be set to low level at the same time, so that the data of word 1 appears on the data bus, and P1.0 and P1.1 are output after XORing by U11 to make the G terminals of U5 and U6 high level, thereby locking the data into U5 and U6. Since the output after RD is ORed with Y7 and Y6 is connected to the OE gates of U5 and U6, when U1 performs a read operation, the OE gates of U5 and U6 should be opened successively to read the data. The receiving procedure is as follows: (taking receiver 1 as an example). The two-way reception of DEI1016 may produce the phenomenon of simultaneous reception. That is, when the above two channels share an interrupt source, if one channel has applied for an interrupt and entered the receiving program, the data received by the other channel at the same time may be blocked. The solution is: after entering the interrupt program, query the status of the other channel DR during the data receiving process. Of course, if each channel uses an interrupt source separately, the effect will be better.

clr p1.2 ; Set DEI1016 SEL = 0, read word 1

clr p1.0 ; set DEI1016/OE1=0

SET ｂ ｐ１．１ ； SET DEI1016 / ＯＥ2 = 1

nop

mov dptr, #e000h

movx a, @dptr ; read the lower 8 bits of word 1 into

mov 10h, a

mov dptr,#c000h

movx a, @dptr ; read the high 8 bits of word 1 into

mov 11h, a

SET ｂ ｐ１.２ ; Set DEI1016 SEL = 1, read word 2

nop

mov dptr, #e000h

movx a, @dptr ; read the lower 8 bits of word 2 into

mov 12h, a

mov dptr,#c000h

movx a, @dptr ; read the high 8 bits of word 2 into

mov 13h, a

SET 1.0 ; Set DEI1016/OE1=1

SET ｂ ｐ１．１ ； SET DEI1016 / ＯＥ2 = 1

SET 1.2 ; Set DEI1016's SEL = 1

4 Conclusion

In fact, the interface circuit of AT89C52 and DEI1016 can be applied to other 16-bit data bus interface circuits after improvement. If ISP devices are used to replace latches and their gate circuits, the area of ​​the circuit board can be greatly reduced.