Design of data storage system based on NAND Flash

introduction

Although traditional storage devices have the advantage of low price, they often have limited storage space, many test parameters, high acquisition rate, and complex environment in high-temperature, high-speed, and high-impact test environments. In order to obtain accurate test data, higher requirements are also placed on the performance of storage devices, such as high storage speed, large storage capacity, small and light, and impact resistance. At this time, traditional storage devices cannot complete the storage task of complex environment test data. To solve this problem, this paper designs a data storage system based on NAND Flash. The system adopts the flexible, efficient, and low-cost solution SOPC proposed by Xilinx, integrates the general RISC processor MicroBlaze and the user-designed specific function logic circuit into the FPGA, and stores data in the NAND Flash storage device under the control of the FPGA, realizing an embedded data storage system based on the SOPC solution.

NAND Flash storage device is a type of Flash memory, which uses nonlinear macrocell mode internally, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. NAND Flash memory has the advantages of small size, low power consumption, fast read and write speed, etc. It is suitable for storing large amounts of data and is widely used in embedded products such as digital cameras, MP3, and USB flash drives.

1 Overall system design

The structural block diagram of the data storage system based on NAND Flash is shown in Figure 1.

This paper uses Samsung's NAND Flash chip K9F4GOSUOA as the main storage device, Atmel's ATmega162 and Xilinx's Spartan-3E series XC3S500E as the control device, and combines the timing configuration of NAND Flash read, write, erase and other operations. The A/D conversion chip uses Maxim's MAX1308. In addition, in order to realize the transmission of data from the acquisition device to the PC via the USB bus, the FT245R chip of FTDI is used as the USB2.0 interface controller; and a special "multi-channel data analysis software" is designed and developed on the LabVIEW platform for the later analysis and processing of data in the storage system.

2 NAND Flash Array Storage Principle

Flash memory programming is in pages. When programming a single page of a single-chip NAND Flash, the command latch signal CLE writes the programming operation command to the port, the address latch signal ALE writes the operation block address, and after transferring 2 KB of data to the data register, the Flash enters the programming stage. At this time, its port R/B signal is pulled low, indicating that the Flash is in a busy working state until the programming is completed. During this period, the system cannot perform any operations on the Flash. Generally, the typical time of this stage is 200μs. If a single-chip Flash memory is used for storage, data can only be written after the programming is completed. Such a large amount of time is consumed in the programming process, which greatly limits the improvement of the system storage speed.

In order to improve the system's storage capacity and storage speed, the system uses 8 NAND Flash memories, with 4 pieces in each group forming a storage array with a bus width of 8 bits. In addition to setting an independent chip select signal CE, the other control signals are shared by the 8 pieces; the two groups of Flash share the data bus, and when storing data, the first group of Flash is first stored, and the second group is stored after the first group is stored. The Flash array storage structure is shown in Figure 2.

From the above analysis, it can be seen that the process of Flash data storage consists of write address commands, data transmission and Flash programming stages. In order to improve the overall storage speed of the system and reduce the system waiting time, according to the characteristics of NAND Flash memory, the Flash storage array is designed by drawing on the time division multiplexing technology, that is, the programming time of the previous Flash is used to operate the next Flash, and the data is loaded into the data register of the flash, and so on to realize the four-level pipeline. In this way, the entire system can load data to the Flash at any time, ensuring the continuity of data storage. [page]

Time Division Multiplexing (TDM) divides the transmission signal according to its time. It allows different signals to be transmitted at different times, and divides the entire transmission time into many time intervals. Each time slice is occupied by one signal, which can not only ensure the independence of each transmission signal, but also improve the transmission efficiency of the system. Based on this principle, the programming time of Flash can be regarded as a fixed time period, which is divided into 4 time slices. In these 4 time slices, data is loaded to the 4 Flash in a module of the Flash array respectively. The high-speed data stream input into the storage system is regarded as a time slice of the time required to transmit a group of data.

The specific operation is as follows: first load data into the first Flash memory, and the Flash enters the programming state; during the programming period of the first Flash, load data to the second Flash; when the second Flash enters the programming state, load data to the third Flash; execute in sequence, and after the overall operation is completed, all four Flashes have loaded data. At this point, the programming of the first Flash has been completed and is in a ready state, and new data can be written, which is equivalent to the programming time of the Flash memory being 0. In this way, the continuous transmission of data in the Flash array can be achieved, improving the overall speed of the system.

The principle of multi-chip Flash time-division multiplexing data storage is shown in Figure 3.

3 System Hardware Implementation

The system uses Xilinx's FPGA for SOPC development, the processor uses MicroBlaze soft core, and configures corresponding parameters to make the standard IP core adapt to the system designed by the user. Combined with peripheral power supply circuit, USB interface circuit, and program configuration circuit, it constitutes a stable data storage system.

3.1 Implementation of FPGA System-on-Chip

The main functions of the FPGA program are: software control to start storage, under the control of the control logic, the data after the front-end A/D conversion is first stored in the internal FIFO cache, and at the same time, DMA is started to store the data in the cache into the external NAND Flash storage array. This paper uses VHDL language to write programs and realizes high-speed data storage and transmission control on the FPGA chip.

3.2 USB interface circuit module

USB devices are mainly used to realize the communication between SOPC system and host and data transmission in online mode. The USB chip uses FT245R launched by FTDI. This interface can convert USB interface signals into 8-bit parallel signals and upload them to MicroBlaze processor with a clock frequency of 150 MHz for analysis and processing; and convert the data sent by the processor into standard USB interface data and transmit it to PC, completing the communication between SOPC system and PC. The USB interface circuit is shown in Figure 4.

3.3 FPGA Configuration Circuit Module

This system uses the master serial configuration mode in the FPGA configuration circuit. The external configuration chip uses the XCF04S series PROM serial configuration chip. When the system is powered on, the chip uses the active configuration mode to implement the hardware configuration of the FPGA in the system. Through the high-speed serial interface, the configuration of the entire chip can be completed in a very short time.

3.4 Power Module

The power module can not only provide various high-performance power outputs for various components of the system, but also select appropriate bypass and decoupling capacitors to filter out various interference signals to ensure the stable operation of the system. The power module of this system uses TI's TPS75003 chip and configures the corresponding peripheral circuits to achieve accurate conversion from 5 V input voltage to 3.3 V, 2.5 V and 1.2 V output voltage.

4 System Verification and Analysis

After the system's software and hardware program design is completed and the BIT stream file is generated, it is downloaded to the FPGA circuit board and combined with the dedicated software in the PC to verify the system function. [page]

4.1 NAND Flash Operation Verification

In the process of data storage hardware system design, the quality of user IP core design determines the success or failure of the entire system design. The system IP core design integrates Flash controller, DMA controller, and data and address FIFO. In order to verify whether the IP core can work properly, the Flash operation verification is carried out. The timing diagram of reading the Flash memory ID number captured by the oscilloscope is shown in Figure 5. Among them, channels 0~4 represent the CE (chip select), ALE (address latch), CLE (command latch), RE (read), and WE (write) signals of Flash respectively. The ID numbers of the 4 Flash chips in the Flash array in the figure are all EC DC 10 95 54, which is consistent with the actual Flash ID. Experiments have proved that the ID number of the Flash memory is accurate.

4.2 Document Registration Form Verification

In the experiment, a file registration table with marked data features is stored in a specific location of the Flash memory. The application reads the information in the file registration table and transmits the corresponding data to the PC for later analysis. The storage content of the file registration table includes: file name, number of experiments, length of stored data, the first and last addresses of this storage, and the first address of the next storage, etc.

Figure 6 shows the file registration table information of a storage experiment. The first 8 bytes in the figure are the file name, followed by the number of experiments and the number of data channels. The storage length in this experiment is 50 MB, and the storage head address and storage tail address are 0x0115 and 0x0178 respectively. Since the storage strategy used is 4-chip pipeline storage, each Flash block is 128 KB, and each large block in the 4-chip module is 512 KB (128 KB×4), it can be calculated that the stored data is 512 KB×(0x0178-0x0115+1)=50 MB. This is consistent with the specified length of the stored data, indicating that the storage system is correct and reliable.

4.3 Data Storage Verification

After the system is built, the sine wave signal generated by the signal generator is collected and stored in the laboratory environment. The data stored in the NAND Flash chip is uploaded to the PC through the USB interface. The "multi-channel data analysis software" designed and developed based on LabVIEW is used for analysis and processing. The obtained analog signal and system switch digital signal waveforms are shown in Figures 7 and 8.

By comparing the original signal, it is found that the system can quickly and without distortion collect and store the waveform data generated by the signal generator, and can use different sampling rates to record the system switch digital signal information, with high reliability.

Conclusion

This paper designs a data storage system based on NAND Flash, which greatly improves the storage speed of Flash chip through time-division multiplexing pipeline operation. Experiments show that the system can quickly and accurately record the waveform data generated by the signal generator, and has the advantages of stable and reliable performance, simple operation, and strong overload resistance.