Low-cost PCI arbiter logic expansion design

The PCI bus is one of the most popular control buses today. It is widely used in computers, and many solutions in embedded devices currently include the PCI bus. In the PCI system application of multiple master devices, arbitration authorization signals must be provided for each master device. In order to make PCI devices more convenient to use in embedded systems, this paper introduces a design method for the logic expansion of a low-cost PCI bus arbiter based on Freescale MPC5200B. This method can expand the number of master devices on the PCI bus on the basis of the existing PCI arbiter, thereby meeting the design requirements of multiple PCI devices and improving the scalability requirements of the system. It has good application prospects in terms of volume, function, cost and many other aspects.

MPC5200B

Freescale's MPC5200B is a high-performance microprocessor based on the PowerPC architecture. It has the characteristics of 760MIPS, floating point unit (FPU), low power consumption, etc. The processor adopts the high-performance e300 core, integrates high-performance storage controller, interrupt controller, DMA controller, PCI controller, Ethernet controller, and rich interfaces such as USB, CAN 2.0A/B, I2C, etc. Its structural block diagram is shown in Figure 1.

Figure 1 MPC5200B Block Diagram

The MPC5200B can provide fast data throughput and processing. The integrated BestComm DMA controller can reduce the load of the main e300 core to transmit I/O intensive data. The integrated double data rate (DDR) memory controller has an effective memory bus speed of 266MHz, which can achieve high-speed data access. The high-speed PCI interface supported by the BestComm DMA controller and DDR memory can achieve high-speed data input and output.
The MPC5200B has an integrated PCI bus arbitrator, but its arbitration only supports two external PCI master devices (including the PCI module of the MPC5200B). In order to increase the PCI master devices, we must expand the PCI arbitrator.

PCI bus arbitration

The PCI bus is a shared bus that can connect multiple master devices, but due to the exclusive nature of data transmission, only one master device can occupy the bus at any time. Therefore, in order to effectively utilize the PCI bus bandwidth, an arbitrator must be set on the bus.

Each PCI device with master device function must provide two arbitration-related signals: REQ# (bus request signal) and GNT# (bus grant signal). The device that needs to initiate a PCI transfer transaction sends out a REQ# signal, and the PCI bus arbiter gives a GNT# signal after arbitration. The PCI device that receives the GNT# signal will start operating after the next bus idle.

The arbitration process of PCI bus arbitration can be completed during PCI transmission and does not occupy the bandwidth of the PCI bus. This is called implicit arbitration: that is, the device that needs to initiate a PCI operation can issue a request REO# at any time, and the PCI arbiter immediately approves the request and gives GNT#. However, the actual transmission process must wait until the current transmission is completed and the line is idle before it can start. [page]

Specific design and simulation Taking

the expansion of two master PCI devices of MPC5200B as an example, according to the PCI arbitration principle and the MPC5200B PCI controller interface, the logical expansion method is shown in Figure 2. The logic unit is the part elaborated in this article.

Figure 2 MPC5200B PCI arbitration logic expansion diagram

MPC5200B contains an on-chip PCI bus arbiter, and now its arbitration function needs to be expanded externally to meet the needs of multi-master PCI devices.

For the external PCI master device, there are two pairs of REQ# and GNT# signals that need to communicate with the MPC5200B on-chip PCI arbiter; for MPC5200B, the logic unit is its one-to-one master PCI device, and the communication signal is the related PCI bus control signal. The logic unit circuit is shown in Figure 3.

Figure 3 MPC5200B PCI arbitration logic expansion circuit

Figure 3b MPC5200B PCI arbitration logic expansion circuit (continued)

After the PCI bus reset signal resets the logic circuit, if there is only one bus request, the corresponding bus authorization signal MASTER_GNT is output through the MUX controlled by the bus request, realizing the bus "request-authorization" process.

If two PCI peripherals generate bus request signals REQ0# and REQ1# at the same time, the DR (Dual Require) signal cooperates with PCI_PRAME and PCI_CLK to lock the update of the NG (Next Grant) signal until the current frame transmission is completed.

As can be seen from Figure 4, the simulation environment simulates the situation of one device applying and two devices applying at the same time, and gives the bus authorization signal (GNT) respectively, verifying the correctness of the arbitrator expansion logic.

Figure 4: MPC5200B PCI arbitration logic expansion circuit simulation

Conclusion

PCI bus protocol is very abstract and has complex timing logic. This paper uses simple logic design to implement PCI arbiter expansion, which has been implemented in CPLD and successfully applied to PCI arbiter logic expansion of MPC5200B.

References:
1. MPC5200B User's manual. Rev.1
2. PCI Local Bus Specification. Rev 2.2