Design of TFT LCD IP and driver based on embedded Linux

Overall system design

The overall design block diagram of this system is shown in Figure 1.

Figure 1 System Block Diagram

The Nios II processor creates a frame buffer in SDRAM, which can be either single buffer or double buffer. Take single buffer as an example. The processor stores a frame of image data (640×480×2Bytes, RGB565, 16bit) in the frame buffer, then writes the first address of the frame buffer to the LCD controller and starts the LCD controller. The controller automatically reads data from the first address transmitted and outputs it in the format of TFT. The modules in the figure are connected together by Avalon Bus. Avalon Bus is a simple bus structure. The Nios II processor and various peripherals are connected together through Avalon Bus. As can be seen from Figure 1, the SDRAM Controller as a slave is controlled by the Processor and the LCD Controller respectively. In order to resolve bus conflicts, the Avalon Bus automatically adds an arbitration module such as Arbitrator to the conflicting interface to reasonably allocate bus time. The user changes the amount of bus time allocated to each module by changing the weight of each module. In this system, the SDRAM Controller is the key to the performance of the entire system. Assuming the SDRAM clock frequency is 100MHz, the total data bandwidth of 16-bit SDRAM is 200MByte/s, and the 640×480×2Bytes×60Hz TFT LCD will occupy about 36MByte/s of bandwidth, which has a great impact on the processor that also has to handle other tasks.

FPGA Implementation of LCD Controller

Avalon Bus Slaver is implemented from the bus interface module

The Avalon slave bus interface is responsible for the interface control between the processor and the LCD controller. The LCD controller acts as a slave device in the entire system. NIOS II sets the control register through this interface to control the LCD.

The LCD slave module has four 32-bit readable and writable registers, which are used to control the operation of the LCD controller and indicate its working status.

Avalon Bus DMA Master host device interface module implementation

The Avalon Bus DMA Master is responsible for reading the data in the SDRAM and writing it into the FIFO according to the instructions of the control module. Its core part is the DMA address accumulator. When the conditions are met, the address accumulator starts to accumulate in units of 4 at a clock of 100MHz to generate the address for reading the SDRAM. After reading a frame of data, it automatically resets to the first address and continues to accumulate.

The master device interface adopts a delayed master device read transfer mode. In this transfer mode, the master device can initiate the next read command even if it has not received the valid data from the previous time. When the waitrequest signal is invalid (low level), the master device can continuously initiate read commands. When the waitrequest signal is valid (high level), the master device starts waiting until it becomes low level. When the readdatavalid signal is valid (high level), it means that the read data is valid. At this time, the master device can latch the valid data on the data port. The flush signal is not used here. The flush signal will clear all the previous unfinished read commands. The Avalon bus ensures that the output order of the data is consistent with the order required by the master device (that is, consistent with the output order of the master device address). The readdatavalid signal can be used as the wrreq signal of the FIFO, so that the read data can be directly written into the FIFO. When the current address is equal to the tail address, the accumulator is reset to restart the accumulation from the first address. The address accumulator code module is shown in Figure 3. [page]

Figure 2 LCD BSF diagram

Figure 3 BSF diagram of device interface module

FIFO module implementation

The function of FIFO is to cache the image data output by DMA to match the output speed of the timing control module. The FIFO size is temporarily set to 4096×16bit. In actual design, it can be adjusted appropriately according to system requirements and resource conditions. The principle is to set the FIFO size as large as possible if system resources allow.

The FIFO is written by the DMA controller with a write clock of 100MHz; the data is read out by the timing generation module of the LCD controller with a read clock of PCLK, which is the LCD pixel scanning frequency, usually 25MHz. Under the action of independent write clock and read clock, the FIFO can provide rdusedw[11:0] signal to indicate the used capacity in the FIFO. The system can set an upper limit and a lower limit. When the amount of data in the FIFO is higher than the upper limit or lower than the lower limit, the controller suspends DMA transmission or starts DMA transmission to ensure system performance.

In this application, connect wrclk to the system clock (100MHz), wrreq to master_readdatavalid, and data to writedata to complete the DMA data write operation; connect rdclk to 12.5MHz (because the TFT clock is 25MHz, the data width is 16bit, and the FIFO width is 32bit, so half of the clock 12.5MHz is used to read the FIFO, and then the high 16bit and low 16bit of 32bit are output in sequence), rdreq is controlled by the timing generation module, and a data can be read out to q at each rising edge of rdclk. Connect aclr to ~reset_n to complete the reset operation. Of course, all signals are controlled by controller_GoBit.

The FIFO design uses the fifo macro module that comes with Quartus II to automatically generate the required modules for calling.

LCD timing generator design module implementation

The timing generator is used to generate the timing required by TFT and output the image data in a specific timing. The key to the design of each controller is the timing design. This article specifically focuses on Mitsubishi's AA084VC05 LCD screen. Figure 4 and Figure 5 are its timing diagrams. [page]

Figure 4 Horizontal timing diagram

Figure 5 Vertical timing diagram

LCD timing generator uses DCLK as the clock reference. This DCLK is the PCLK mentioned above, that is, the pixel clock. The data of each pixel is driven into the LCD with this clock. Figure 4 shows the horizontal scanning timing of AA084VC05, where DATA is an 18-bit data signal (only 16 bits are used in this design), DENA is a data valid signal, high level is enabled, and its effective width THA is 640 DCLKs; HD is a horizontal synchronization signal, low level is effective, and its effective width TWHL is 96 DCLKs. After scanning a row of 640 pixels, the controller will drive HD to be effective, insert THFP (Horizontal Front Porch) of 16 DCLKs before HD is effective, and insert THBP (Horizontal Back Porch) of 144 DCLKs after HD is effective, and then start scanning the next row. In this way, the typical value of the frequency FH ​​of the row scanning signal is 31.5KHz. The read FIFO signal arrives one clock beat earlier than the DENA signal and ends one clock beat earlier because the FIFO has a clock beat delay.

The vertical scanning timing of AA084VC05 is similar to the horizontal scanning timing. This timing uses HD as the clock reference, where VD is the vertical synchronization signal (frame synchronization). After each frame (480 lines) is scanned, the controller will drive VD to be valid (low level), and the effective width TWVL is 2 HD. Similarly, before VD is valid, TVFP (Vertical Front Porch) is inserted with 10 HD, and after VD is valid, TVBP (Vertical Back Porch) is inserted with 35 HD. In this way, the typical value of the vertical scanning signal frequency FV is 60Hz.

The timing generator is implemented by a state machine. Since the parameters of the controller are relatively large, in order to facilitate the observation of simulation results, this paper has made some processing on these parameters (reduced by multiples).

Conclusion

This paper designs and implements a simple TFT LCD controller based on Avalon bus, which can realize 640×480 color graphics display with a color depth of 16 bits. It can be applied to various TFT LCDs and can also be rewritten as a VGA controller, which has great flexibility. According to the designed controller, the corresponding Frame buffer driver under Linux is written. The development of the interface environment is well realized and can be used in many electronic products of handheld devices. The biggest feature of this design is that it has strong portability, and both the design of the controller and the design of the Frame buffer driver are very flexible.