Design of digital repeater system based on AD6655

1 Introduction

With the rapid development of mobile communication services, repeaters, as important equipment for improving the weak signal blind spots of mobile networks, are widely used in 2G mobile networks with the advantages of low investment, simple structure, convenient and flexible installation, etc. However, the 2G network still uses repeaters with analog devices. For the third-generation mobile communication system, various countries have proposed a variety of different standards, but it is very difficult to unify the standards. The future mobile communication system has problems such as multi-frequency, multi-mode, multi-system and multi-standard, which limits the intercommunication and compatibility of various devices. Therefore, there is a real demand for the application of software radio technology in repeaters. In order to improve the cost-effectiveness of 3G repeaters, it is a better solution to unify the hardware platform of 3G repeaters with digital technology. Here, a general and scalable hardware platform design with AD6655 as the core of the digital intermediate frequency signal acquisition system is proposed.

2 AD6655 Introduction

2.1 Performance characteristics

AD6655 is a highly integrated diversity receiver from ADI, with a low-latency peak detector, RMS signal power monitor, two 14-bit A/D converters, and a digital down-converter (DDC). AD6655 uses 1.8 V and 3.3 V power supplies; when operating in a bandwidth of 32.7 to 70 MHz and a sampling rate of 150 MS/s, the SNR is 74.0 dBc; and in a bandwidth of 70 MHz, the SFDR is 84 dBc. Therefore, the device is suitable for receiver systems of various standards such as TD-SCDMA, WCDMA, CDMA2000, WIMAX, and GSM.

2.2 Internal structure

The internal structure block diagram of AD6655 is shown in Figure 1. AD6655 contains a rich signal monitoring system, each channel has a 4-bit signal detection bit, allowing the monitoring data to be output in serial mode.

The main functional modules of AD6655 are 14-bit A/D converter and DDC. The signal enters the A/D converter through the sample-and-hold device, then down-converts through the DDC, and finally outputs the data through the output buffer. The DDC includes modules such as 32-bit numerically controlled oscillator (NCO), low-pass/high-pass half-band filter, FIR filter and fDAC/8 NCO. Except for the half-band filter, the other four modules are optional units. Therefore, by configuring the register, the DDC has 5 working modes: half-band filter working mode, outputting real signal data; half-band filter + FIR filter, outputting real signal data; 32-bit NCO + half-band filter mode, outputting complex signal data; 32-bit NCO + half-band filter + FIR filter; outputting complex signal data; 32-bit NCO + half-band filter + FIR filter + fDAC/8 NCO mode, outputting real signal data. Users can select the appropriate working mode according to the frequency, spectrum width and output signal requirements of the input signal. [page]

3 Digital Repeater System Design

The digital repeater is a 3G base station extension system with digital pre-distortion, multi-carrier and digital functions. It can realize the long-distance digital transmission of 3G base station RF signals with large capacity and large dynamic range, and provide flexible and diverse rapid networking methods. It supports multi-band and open architecture, realizes remote upgrade and distributed network construction, and can effectively improve network performance and reduce the operating costs of network construction.

3.1 Introduction to Digital Repeater

The digital repeater is mainly composed of two parts: radio frequency and digital intermediate frequency. The radio frequency part includes: low noise amplifier, analog radio frequency receiver, analog radio frequency transmitter, multi-carrier power amplifier; while the digital intermediate frequency includes: A/D converter, D/A converter, digital up/down conversion, digital filtering and diversity reception, digital pre-distortion, peak-to-average ratio reduction (CFR) module.

Digital up/down conversion realizes functions such as signal spectrum shifting, sampling rate conversion, and channel filtering. The CFR module is used to reduce the peak-to-average ratio of 3G signals. In 3G communication systems (such as WCDMA communication systems), the peak-to-average ratio of signals is relatively high, generally up to 10-14 dB. Since most power amplifiers are nonlinear and have limited dynamic range, this requires that the peak-to-average ratio of the signal before D/A conversion should be ensured to be 5-8 dB. The CFR module is used to reduce the peak-to-average ratio of the signal, prevent intermodulation interference and spectrum leakage between subcarriers, improve system performance, and increase the working efficiency of power devices. The adaptive digital pre-distortion module can eliminate the distortion caused by the nonlinearity of the power amplifier.

3.2 System Hardware Design

This system design is mainly based on the design concept of software radio, aiming to design a universal hardware platform with the characteristics of modularity, openness, and scalability, which can achieve smooth transition between different carriers and easy upgrade between different standards. The block diagram of the digital repeater system design is shown in Figure 2.

AD6655 collects the intermediate frequency signal transmitted by the analog mixer and transmits the digital signal to the FPGA. The single-chip microcomputer (MCU) uses ATmega16L to realize the configuration and communication control of functional modules such as A/D converter, D/A converter, and clock. FPGA uses Xilinx's Virtex-4 SX35, which has the characteristics of high operating frequency and powerful DSP function. As the core of the whole system, FPGA completes the functions of digital down-conversion, digital up-conversion, and peak-to-average ratio reduction.

Different sampling techniques need to be selected for receivers with different applications, and then the best sampling frequency and intermediate frequency are determined. In view of the characteristics of 3G signal bandwidth and high operating frequency, such as the WCDMA signal transmission frequency band of 2 110-2 170 MHz and the four-carrier bandwidth of 20 MHz, bandpass sampling needs to be selected. Reasonable selection of sampling frequency and IF frequency is conducive to simplifying the design of anti-aliasing filter before A/D conversion and improving frequency resolution. Based on the comprehensive consideration of AD6655 performance, the system design sets the sampling frequency to 122.88 MHz and the intermediate frequency to 153.6 MHz.

The DDC in the AD6655 performs a preliminary down-conversion of the signal within the entire passband, reducing the requirements for the FPGA signal processing clock of the signal within the passband. Since this system design uses bandpass sampling technology, the signal within the passband will be mirrored at a frequency domain greater than an integer multiple of fs. When the sampling frequency is 122.88 MHz and the intermediate frequency is 153.6 MHz, the mirror image in the first Nyquist interval is selected, and its center frequency should be 30.72 MHz. In order to achieve the best effect of the HB filter, the center frequency of the signal needs to be converted to zero intermediate frequency, and the 32-bit NCO frequency control word NCQ_FREQ is 0x40000000. The use of a 19th-order HB filter with a polyphase structure in combination with a 66th-order FIR filter can achieve a good low-pass effect, as shown in Figure 3.

It is important to note that the HB filter limits the signal bandwidth. At a sampling clock of 122.88 MHz, the HB filter bandwidth can reach 24 MHz. At the same time, the HB filter is a downconverter with a decimation rate of 2. The signal spectrum of the last stage of the DDC fDAC/8 NCO is moved to 15.36 MHz after low-pass filtering. [page]

Figure 4 is the actual application circuit of AD6655, which uses a broadband transformer to realize the conversion between single-ended signal and differential signal. In this way, even harmonic components and common-mode interference signals (such as noise introduced by power supply and ground) can be filtered out at the analog signal stage. This system design provides two methods to add a DC bias to the analog signal input of the A/D converter: the first method is to provide the CML signal provided by the A/D converter, and the DC bias is fixed; the other method is to provide the analog power supply voltage divided by R507 and R513, and the DC bias can be modified according to the needs. It is recommended that the DC bias is equal to AVDD/2.

In the circuit, R500, R501 and C482 form a simple anti-aliasing filter. The specific value can be calculated according to the actual intermediate frequency. It should be noted that the application circuit does not provide a decoupling capacitor. In actual application, the necessary decoupling capacitor needs to be added.

AD6655 configures register parameters through the SPI bus of MCU. AD6655 uses chip select signal (CSB), serial communication clock (SELK), and serial communication data output/input port to realize system control (SDIO). First, configure register 0x00 to 0x3C, and then configure it to 0x18 to achieve software reset of AD6655 register; when there is no analog signal access, if it is found that the digital signal after conversion by AD6655 is not 0x2000, it is necessary to configure register 0x10 to compensate for DC offset error until it meets the requirements; configure registers 0x102, 0x103, and 0x11D to 0x01, 0x01, and 0x07 respectively, so that AD6655 works in the fifth working mode; by configuring registers 0x11E~0x121, set the 32-bit NCO frequency to 30.72 MHz, and the corresponding frequency word is 0x40000000.

4 Test Results

4.1 Test plan

The IF input signal is a four-carrier WCDMA IF signal generated by Agilent E4438C, with a center frequency of 137.88 MHz. The four carrier frequencies are set to 130.38 MHz, 135.38 MHz, 140.38 MHz, and 145.38 MHz, respectively, and the input signal amplitude is 0 dBm. After the signal passes through the IF board of the digital repeater, the IF signal is connected to the spectrum analyzer Agilent E4408B to observe the signal spectrum and WCDMA signal performance indicators.

4.2 Test Results and Analysis

Figure 5 shows the spectrum of the intermediate frequency output signal after the WCDMA intermediate frequency signal passes through the system board. As can be seen from Figure 5, the number of carriers and frequency points of the output signal meet the setting information. The output frequencies are (122.88+7.5)MHz, (122.88+12.5)MHz, (122.88+17.5)MHz, (122.88+22.5)MHz, and the ACLR is about 45 dB@5MHz and 45 dB@10 MHz. At the same time, the average EVM of each frequency point is measured to be 4.68%. Generally speaking, the EVM of the RF circuit is 3% to 5%. In this way, after the digital intermediate frequency and the RF are cascaded, the EVM is still less than 12.5%. Therefore, the EVM value of the system can meet the index requirements.

From the functional point of view, the design scheme realizes the basic functions of the digital intermediate frequency system of the digital repeater; from the performance point of view, although the scheme meets the performance requirements, its performance still needs to be optimized. Since the data volume of a single carrier of CDMA2000 is smaller than that of WCDMA, the requirements for the receiver noise coefficient and A/D conversion are also lower than those of WCDMA, so as long as the parameters are reconfigured and the corresponding program code is downloaded to the FPGA, the CDMA2000 multi-carrier digital intermediate frequency system can be easily realized. The hardware platform of this system is also suitable for GSM digital intermediate frequency, which can realize the expansion and upgrade of more carriers of GSM digital intermediate frequency.

5 Conclusion

AD6655 is a 14-bit high-performance broadband analog-to-digital converter with a sampling rate of up to 150 MS/s. It integrates NCO, HB filter, FIR digital filter, and has multiple working modes and good AC and DC performance. Therefore, AD6655 can be used in communication and image acquisition systems, and is suitable for signal acquisition systems of digital repeaters in mobile communication systems of different standards.