High-speed data acquisition card based on ARM

1 Introduction

With the increasing requirements for data acquisition in modern industrial production and scientific research, high-speed data acquisition is required in some high-speed and high-precision measurements such as transient signal measurement and image processing. Currently, the common high-speed data acquisition cards are generally PCI cards or ISA cards, which have the following disadvantages: complex installation, expensive, limited by the number of computer slots, addresses, and interrupt resources, poor scalability, and in some test sites with strong electromagnetic interference, it is impossible to specifically perform electromagnetic shielding on them, resulting in distorted collected data.

This data acquisition card uses Philips' LPC2142 microcontroller (based on the ARM7 core, with a built-in wide-range USB 2.0 serial communication interface), which effectively solves the defects of traditional high-speed data acquisition cards.

2 Principle of ARM-based data acquisition card

This system is mainly composed of dual-channel analog/digital converter AD9238, ARM microcontroller and FPGA device EP1C3T100. The structural block diagram is shown in Figure 1. AD9238 has two channels, A and B. The differential amplifier at the front end amplifies the analog signal and sends it to AD9238, which converts the analog signal into a 12-bit digital signal and sends it to the FIFO buffer in the FPGA. The interface made by LabVIEW equipment sends control instructions to LPC2142, which reads the data in the FIFO buffer and sends it to the host through the USB port. The host can also select the sampling frequency, sampling starting point, analog signal conditioning and read precision frequency measurement data through the interface menu.

3 Data Acquisition Card Hardware Structure

3.1 AD9238 Introduction

AD9238 is a 12-bit, dual-channel analog-to-digital converter launched by Analog Devices (ADI). The converter is divided into three models, with sampling rates up to 20 MS/s, 40 MS/s and 65 MS/s respectively. It provides the same excellent dynamic performance as a single-channel A/D converter, but has better anti-crosstalk performance than using two single-channel A/D converters; it uses a single 3 V power supply (2.7 V ~ 3.6 V); Rsn = 70 dBc; Rsfd = 85 dBc; ENOB = 11.3 b; 500 MHz 3 dB bandwidth for differential input; with on-chip reference voltage and SHA; 1 ~ 2 Vpp analog input range; output data format is offset binary code or binary complement code. [page]

The two channels of AD9238 use one AD8138 as the op amp driver. The two intermediate frequency analog signals of I/O are converted into differential signals through two AD8138s and sent to the A/D converter (pins 2, 3, 14, and IS).

High-speed ADCs are very sensitive to the duty cycle of the clock, and generally require a duty cycle of 50% (±5%). AD9238 provides a separate clock for each channel (pins CLK_A and CLK_B). When the sampling clocks of the two channels are of the same frequency and phase, the performance is good. When the two channels are not synchronized, the performance will deteriorate.

This data acquisition card uses a 40 MHz AD9238, and the single or dual channel selection and conversion frequency can be controlled by software.

3.2 Cyclone Series FPGA Devices

Due to the special requirements of the high-speed data acquisition system, Altera's Cyclone series devices were selected from a variety of FPGA devices. The Cyclone series is based on the advanced Stratix process architecture and provides extremely high cost performance for high-speed applications. In addition, the internal RAM memory of the Cyelone series devices can generate FIFO buffers to provide buffer space for high-speed sampling.

Altera's Quartus II software is an easy-to-use comprehensive development tool that integrates all tools and third-party software interfaces involved in Altera's FPGA/CPLD development process. It has a user-friendly interface and provides convenient conditions for design.

Here, the FPGA device mainly completes tasks such as data caching, equal-precision frequency measurement, sampling frequency division and trigger control.

3.3 Application of FPGA in trigger control

Since this data acquisition card is a high-speed cache type with limited cache space, it cannot adopt the continuous acquisition mode, but the triggered acquisition mode. In order to improve the applicability of the data acquisition card, not only can it acquire periodic signals, but also can acquire trigger signals, and can also manually trigger the acquisition, the author added a trigger point capture circuit. The system is mainly composed of AD8561 voltage comparator and FPGA devices. The conversion speed of AD8561 is very high, which can meet the requirement of high enough judgment speed. First, the analog signal is sent to the positive input end of the AD8561 comparator, and the negative input end is connected to the output end of the D/A converter of LPC2142. The output voltage of the D/A converter of LPC2142 is used as the reference voltage of the AD8561 comparator. This reference voltage can be adjusted by writing different values ​​to the register of the D/A converter of LPC2142. This adjustment is finally controlled by the interface made by LabVIEW. When the input signal voltage is higher than the reference voltage, the output end TOUT of AD8561 is pulled high, and the level of TOUT can be latched by inputting a high level to the LATCH end of AD8561. The trigger control circuit diagram is shown in Figure 2.

In manual acquisition mode, TRIENO is low level, TRIEN1 is high level, when the buffer is empty, FWr_FUL is high level, and QSTART is high level controlled by the interface made by LabVIEW, FWr_EN is pulled high for data acquisition. When the buffer is full, FWr_FUL is pulled low and data acquisition stops.

In the input signal trigger mode, TRIEN0 and QSTART are low level. When the buffer is empty, that is, FWr_FUL is high level, and the input signal voltage is higher than the reference voltage of the comparator, TOUT is pulled high, and FWr_EN is pulled high for data acquisition. When the buffer is full, FWr_FUL is pulled low and data acquisition stops. Pull TRIEN1 high to read the cache data.

The acquisition cycle signal is similar to the input signal trigger mode, but TRIEN1 is kept high. When reading cache data, data is acquired after the trigger signal arrives.

4. Software Design of High-Speed ​​Data Acquisition Card

4.1 USB driver programming based on μC/OS-II

μC/OS-II provides the kernel of a multi-tasking real-time operating system. When using this operating system, users are usually required to write their own peripheral device drivers based on μC/OS-II so that the peripheral devices can better serve users under the coordination of the operating system. In order to make the software highly portable and easy to maintain, the author comprehensively considered the USB protocol and the LPC2142 USB hardware conditions when writing the LPC2142 USB firmware, and divided the driver into 5 layers, as shown in Figure 3. The bidirectional lines in the figure indicate that there is data exchange between the user software and the USB firmware, and the unidirectional lines indicate that the upper-layer software calls the lower-layer software, which makes the firmware structure clear.

With the USB driver, users can complete the tasks that the user software needs to achieve on this platform, as shown in Figure 4. The unidirectional line indicates the control of the main task over the read/write task. The main task controls the running state of the read/write task through the semaphore, thereby realizing the reading and writing of the FIFO buffer; the bidirectional line indicates that there is data exchange between each module. In order to speed up the transmission and reception of large amounts of data, this program uses the logical endpoint 1 of the LPC2142USB as the transmission channel for control commands and endpoint 2 as the transmission channel for data. [page]

The main task continuously reads endpoint 1. When receiving a read command from the PC, it activates the high-priority read task's ready semaphore. The read task is awakened and enters the read interrupt service routine, sending the buffer data to the PC via the USB bus. After the sending is completed, the read task's ready semaphore is closed and returns to the main task loop, waiting for the next command from the PC. The write task is similar to this and will not be described again.

4.2 Host software programming based on LabWindow/CVI

4.2.1 Introduction to LabWindows/CVI

As a virtual measuring instrument, the key is to have tool software that is easy to generate a good operating interface and powerful data processing capabilities. The program design of this system was developed using LabVIEW. LabVIEW is a visual programming language based on C/C++ developed by NI Corporation of the United States that is specifically used for virtual instruments and process control. Using the control library provided by LabVIEW (including switches, knobs, charts, etc.), it is easy to design an operating interface that meets actual requirements and is novel and beautiful. In addition, LabVIEW has a strong data processing function. It provides a wealth of library functions for data input interface, data processing (FFT, etc.) and graphic display, which greatly facilitates the development of application software. Figure 5 shows the system operation interface developed by LabVIEW.

4.2.2 Programming

The entire design process consists of four parts: panel design, initialization, data acquisition, data processing and result display. Through careful program design, the predetermined measurement functions are basically completed. And the system operation speed is guaranteed. The functions of each part are introduced as follows.

(1) Panel design: Provides a user-friendly operation interface that complies with the operating habits of conventional measuring instruments.

(2) Initialization: Complete system initialization functions, including resetting, sending working mode words, setting program running parameters, etc.

(3) Data acquisition: LabVIEW cannot directly access the hardware designed by the user. As an open development platform, LabVIEW provides a DLL interface, which allows users to call modules compiled by other software platforms on the LabVIEW platform. It also provides support for object linking and embedding technology (OLE for short). The author used VC++6.0 to write a DLL file and called the file in the LabVIEW environment to achieve data communication between the LabVIEW program and the data acquisition card.

The following are the files related to the DLL compilation project created to read and write USB devices:

DLLBulk.h: Header file that declares variables or function functions.

DLLBulk.def: Module definition file, a text file consisting of several statements describing the DLL module parameters.

DLLBulk.cpp: is the main code file of the DLL.

After compiling each file under DLLBulk.dsw, select Build->Build DLLBulk.dll in the menu bar to generate a DLL file that can be called by LabVIEW.

(4) Data processing and display: Perform various processing on the sampled data in the memory for different measurement purposes. This includes real-time display of signal waveforms, automatic measurement of signal amplitude and time, graph display, deletion of graphs, and playback. Due to space limitations, the program list is omitted here.

5 Conclusion

The entire virtual measurement system described in this paper runs completely under human-computer interaction, and the measurement parameters can be changed at any time and various signal processing can be performed. The system indicators are: the highest sampling rate is 40 MHz, and it can be sampled by 1/2, 1/4, 1/8...1/128 program-controlled frequency division, dual-channel analog input; ADC accuracy is 12 bits; analog input range is 0 V~2V; on-board data cache is 4 KB bytes/channel, and the transmission mode is block transmission. The system can display real-time signal waveforms, signal maximum values, minimum values, and peak-to-peak values, and also provides display graphic file storage, playback, and deletion processing functions.