Automatic calibration and adjustment of calendar clock in single chip microcomputer system

1. Overview
In various detection and control systems, it is necessary to use a calendar clock to control time or record the time when an event occurs. Such as power grid detection systems, street light control systems, etc. However, the defects of the calendar clock often running fast or slow are inevitable. After a long time, a large error will be generated, which will affect the accuracy of control and detection. In order to solve the problem of the accuracy of the calendar clock, we designed a calendar clock that can automatically calibrate and adjust the running speed. It will automatically calibrate once at 12:00 and 00:00 every day, and automatically adjust the running speed of the clock according to the error size of the 12-hour operation. The accuracy of the clock operation can be quite high.
The idea of ​​our design is: use the receiving part of the circuit in the small radio to receive the FM signal with a center frequency of 106.1MHz broadcast by the Central People's Broadcasting Station, demodulate the audio signal, and input the audio signal into two phase-locked loops. These two phase-locked loops track the time signals of 800Hz and 1600Hz respectively. When the time signal is received, an external interrupt is provided to the microcontroller, and the automatic calibration of the calendar clock can be completed by executing the interrupt program. And according to the running error, the digital fine-tuning register and analog fine-tuning register inside the calendar clock chip X1205 are automatically adjusted to adjust the clock running speed within the range of +146ppm to -67ppm.

2. Circuit design

The circuit consists of a single-chip microcomputer AT89C52, a calendar clock chip, an automatic calibration circuit, a 4×4 keyboard and a display circuit.
2.1 Interface between the calendar clock chip X1205 and AT89C52
X1205 is a real-time clock integrated circuit with a clock, calendar, two-way alarm, oscillator compensation and battery switching [1]. I2C bus structure, external 32.768KHz crystal. The address range of the clock/control register is 0000H~003FH.
The functions of each pin of X1205 and its connection with the single-chip microcomputer AT89C52 are shown in Figure 1:
X1, X2: external quartz crystal oscillator terminal.
: When the alarm function is applied, this pin outputs an interrupt signal, and the low level is valid. This circuit adopts a cyclic interrupt mode, interrupting once per second.
SCL: the input terminal of the serial clock provided by the single-chip microcomputer to X1205.
SDA: data input/output pin.
VSS: ground terminal.
VCC, VBACK: the former is the power input terminal, and the latter is the backup power supply. In practical applications, it can usually be connected as shown in Figure 1. Connect a diode between VCC and VBACK, and connect a capacitor between VBACK and ground. Under normal power supply conditions, VCC charges the capacitor. After power failure, the capacitor acts as a backup power supply. After VCC power failure, the backup power supply current is less than 2μA. Capacitor C can also be a 10μF tantalum electrolyte capacitor.

The 2nd, 1st, and 0th bits DTR2, DTR1, and DTR0 of the digital trim register DTR (address 0013H) in the X1205 chip adjust the count value per second and the average ppm error. DTR2 is a sign bit, 1 for positive ppm compensation and 0 for negative compensation. DTR1 and DTR0 are scale bits, DTR1 gives a 10ppm adjustment and DTR0 gives a 20ppm adjustment. These three bits can be used to adjust the compensation within the range of -30ppm to +30ppm. The 5th to 0th bits ATR5, ATR4... and ATR0 of the analog trim register ATR (address 0012H) are used to adjust the on-chip load capacitance. The ATR value is expressed in the form of a complement code, ATR (000000) = 11.0pF, each step is adjusted by 0.25pF, and the entire adjustment range is from 3.25pF to 18.75Pf. Compensation from +116ppm to -37ppm can be provided for the rated frequency. By adjusting DTR and ATR, the compensation can be adjusted within the range of +146ppm to -67ppm.
2.2 Automatic calibration circuit
The automatic calibration circuit consists of a circuit for receiving the signal of China National Radio and an audio phase-locked loop.
The receiving circuit is composed of an FM radio integrated circuit TDA7010T and a small number of discrete components. The TDA7010T integrated circuit contains frequency conversion, intermediate frequency filtering, frequency discrimination and preamplification circuits [2]. It is used to receive the 106.1MHz signal of China National Radio and demodulate it into an audio signal.

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The phase-locked loop is composed of two NE567s and peripheral circuits. The task of this circuit is to lock the two frequency time signals of 800Hz and 1600Hz in the audio signal from the receiving circuit. That is, the time audio signal is converted into a negative pulse signal, providing an external interrupt to the microcontroller, and the clock is automatically calibrated after analysis by the interrupt program, as shown in Figure 2. The figure only shows the part of the two NE567s that locks the 800Hz audio signal. NE567 consists of a frequency detector (PDI), a DC amplifier (A1), a current controlled oscillator (CCO), an orthogonal frequency detector (PDII) and two filters formed by external capacitors C17 and C18 [3]. The capacitor CT and resistor RT = R2 + R3 connected to the 5th and 6th pins of NE567 determine the oscillation frequency f0 (800Hz or 1600Hz) of CCO, f0≈1.1/(RTCT). Select CT=0.1μf. For the circuit with f0=800Hz in the figure, RT≈13.7KΩ; for the circuit responsible for locking the 1600Hz audio signal, which is not drawn in the figure, RT≈6.8KΩ.
When the audio signal received by the 3rd pin of NE567 does not contain a signal with a frequency of f0 (800Hz and 1600Hz) or within the bandwidth, the phase-locked loop can never enter the locked state. If the audio signal contains a signal with a frequency of f0 or within the bandwidth, the voltage output by the discriminator PDI in the phase-locked loop is filtered by the loop filter composed of the internal resistor r2 and the external capacitor C18, and then added to the DC amplifier A1. A1 outputs current to control the change of the CCO oscillation frequency. As a result, the CCO oscillation frequency is close to certain frequencies of the input audio signal within a certain range. After locking, the loop is stabilized. During the capture process of the phase-locked loop, the internal orthogonal frequency detector PDII of NE567 continuously receives the signal output by CCO and the external input signal. As the frequencies of the two signals gradually approach, its output voltage gradually decreases. When the phase-locked loop enters the locked state, this voltage drops to less than Ur, A2 outputs a low level, causing the microcontroller to interrupt.

3. Programming

The main program of the single-chip computer AT89C52 constantly checks whether the data of the hour and minute register unit of X1205 is 11:50 or 23:50. If it is one of them, set the P2.7 pin to 0, turn on the power of the receiving signal circuit, and open the interrupt. There are 6 time signals, each of which is 0.5 seconds long, and the interval between each two sounds is 1.5 seconds. The frequency of the first 5 signals is 800Hz, and the frequency of the sixth signal is 1600Hz. The negative pulse generated by the two-frequency time signals after phase locking by NE567 is input to the interrupt input terminal of AT89C52 through the AND gate. After the interruption, 89C52 measures the pulse width through timer T0. Before and after the time, the radio station often broadcasts music advertisements. There are many audio signals of about 800Hz and 1600Hz in the music, but the frequency of the music changes continuously, and the duration within a certain bandwidth is short. Signals with a pulse width of less than 400ms are regarded as interference signals and are not considered. If an interruption is generated by a 1600Hz audio signal with a pulse width greater than 400ms, and before that, the valid 800Hz time signal has reached 5 times, the display data and the data of the X1205 internal clock register are corrected. And according to the error of the clock operation in the past 12 hours (the error of milliseconds is measured by the timer T1 of 89C52), the data of the digital fine-tuning register and analog fine-tuning register of X1205 are corrected. Set the P2.7 pin to 1, turn off the power of the receiving signal circuit, and turn off the interrupt.
When the main program detects that the data of the hour and minute register unit of X1205 is 12:10 or 00:10, if the P2.7 pin still outputs a low level, it means that the time signal has not been received within 20 minutes, cancel the receiving time signal state and all marks, turn off the power of the receiving signal circuit, and turn off the interrupt. The program flow chart is shown in Figure 3.

4. Conclusion

After long-term experimental observation, the author found that the duration of interference signals is mostly less than 100ms, and those reaching 200ms are accidental. It is safer to limit the interference signal with a pulse width of 400ms. If an interference signal with a duration of more than 400ms appears, a miscalibration with an error of less than 1.5S can only occur if a 1600Hz interference signal is received within 1.5S after receiving 5 800Hz time signals. This possibility is rare. Even if it occurs, it will be recalibrated after 12 hours.

References
[1] X1205 Real Time Clock/Calendar. www.icbase.com
[2] Integrated Circuit Handbook Editorial Committee. Chinese and Foreign Integrated Circuit Data Handbook • Audio Circuit. Beijing: Publishing House of Electronics Industry, 1997: 1372-1373.
[3] Zhang Juesheng, Zheng Jiyu, Wan Xinping. Phase-locked Technology. Xi'an: Xidian University Press, 1994: 118