Design of signal generator based on AD9851

0 引言
直接数字合成(Direct Digital Synthesis—DDS)是近年来新的电子技术。单片集成的DDS产品是一种可代替锁相环的快速频率合成器件。DDS是产生高精度、快速变换频率、输出波形失真小的优先选用技术。DDS以稳定度高的参考时钟为参考源，通过精密的相位累加器和数字信号处理，通过高速D／A变换器产生所需的数字波形(通常是正弦波形)，这个数字波经过一个模拟滤波器后，得到最终的模拟信号波形。
DDS系统一个显著的特点就是在数字处理器的控制下能够精确而快速地处理频率和相位。除此之外，DDS的固有特性还包括：相当好的频率和相位分辨率(频率的可控范围达μHz级，相位控制小于0．09°)，能够进行快速的信号变换(输出DAC的转换速率百万次／秒)。

1 AD9851集成芯片简介
AD9851是在AD9850的基础上，做了一些改进以后生成的具有新功能的DDS芯片。AD9851相对于AD9850的内部结构，只是多了一个6倍参考时钟倍乘器，当系统时钟为180MHz时，在参考时钟输入端，只需输入30 MHz的参考时钟即可。AD9851是由数据输入寄存器、频率／相位寄存器、具有6倍参考时钟倍乘器的DDS芯片、10位的模／数转换器、内部高速比较器这几个部分组成。其中具有6倍参考时钟倍乘器的DDS芯片是由32位相位累加器、正弦函数功能查找表、D／A变换器以及低通滤波器集成到一起。这个高速DDS芯片时钟频率可达180MHz，输出频率可达70 MHz，分辨率为0．04Hz。
AD9851可以产生一个频谱纯净、频率和相位都可编程控制且稳定性很好的模拟正弦波，这个正弦波能够直接作为基准信号源，或通过其内部高速比较器转换成标准方波输出，作为灵敏时钟发生器来使用。
AD9851的各引脚功能如图1所示。

D0~D7: 8-bit data input port, which can load 40-bit control data into the internal register.
PGND: 6x reference clock multiplier ground.
PVCC: 6x reference clock multiplier power supply.
W-CLK: Word load signal, rising edge is valid.
FQ-UD: Frequency update control signal, the rising edge of the clock confirms that the input data is valid.
FREFCLOCK: External reference clock input.
CMOS/TTL pulse sequence can be directly or indirectly added to the 6x reference clock multiplier. In the direct mode, the input frequency is the system clock; in the 6x reference clock multiplier mode, the system clock is the multiplier output .
AGND: Analog ground.
AVDD: Analog power supply (+5 V).
DGND: Digital ground.
DVDD: Digital power supply (+5 V).
RSET, DAC: External reset connection terminals.
VOUTN: Internal comparator negative output terminal.
VOUTP: Internal comparator positive output terminal. VINN
: Internal comparator negative input terminal.
VINP: Internal comparator positive input terminal.
DACBP: DAC bypass connection terminal.
IOUTB: "Complementary" DAC output.
IOUT: Internal DAC output terminal.
RESET: Reset terminal. A low level clears the DDS accumulator and phase delayer to 0 Hz and 0 phase, sets the data input to serial mode, and disables the 6x reference clock multiplier.
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2 System Hardware Design
2.1 Design Scheme
This design scheme adopts the parallel data mode of the AD9851 chip, and the system block diagram is shown in Figure 2. The system consists of 5 parts: single-chip microcomputer circuit, AD9851 chip, low-pass filter circuit, power amplifier circuit and signal output circuit. The single-chip microcomputer circuit uses the general 51 series single-chip microcomputer AT89S52, and the external crystal oscillator frequency is 12 MHz. The low-pass filter circuit uses a passive filter for design. Since the maximum output frequency of this design is 30 MHz, the cutoff frequency of the low-pass filter is around 40 MHz. The reference clock uses a 30.000 MHz active crystal oscillator in a SMD package to provide a high-stability and high-precision signal source for the AD9851 chip.

2.2 Design of low-pass filter circuit
The low-pass filter circuit uses a second-order LC elliptical low-pass filter, which can effectively suppress the output spurious of DDS. The circuit is shown in Figure 3.

2.3 Design of power amplifier circuit
The power amplifier circuit uses AD828 wideband op amp chip. AD628 has two operational amplifiers integrated inside, and the power supply modes include dual power supply and single power supply, which is particularly suitable for high-frequency signal conversion and transmission. In this design, in order to increase the output amplitude of the peak-to-peak value of the signal, the chip power supply uses a dual power supply of positive and negative 10 V DC power supply. This can ensure a relatively high voltage amplitude within the bandwidth of 10 MHz.

3 System software design
3.1 Reset working sequence of AD9851
The reset timing of AD9851 is shown in Figure 4. From the timing, it can be seen that the condition for the reset of the AD9851 chip is a high level at the RESET pin, and the duration is at least trs. According to the time parameters provided in the manual, it can be known that the shortest time of trs is 5 system clocks, and there is no time limit. Because the crystal oscillator of the microcontroller in the system circuit uses 12 MHz. The time required to execute an instruction is 1μs. In order to ensure the reliability of the reset timing, the reset time is 10ms.

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The specific reset subroutine is as follows:

The delay_μs() delay program is used in this subroutine to delay about 1μs.
3.2 The working timing of writing frequency words
The working timing of writing frequency words is the key timing of the AD9851 chip, which is related to the realization of the signal generator function. In parallel mode, the working timing of writing frequency words is shown in Figure 5.

From the timing diagram, it can be seen that
before outputting the frequency control word, W_CLK and FQ_UD must be set to low level; then the five frequency control words are sent out in sequence; when sending data, the working sequence must be strictly controlled. tds is the data setup time, tdh is the data hold time, twh and twl are the duration of the high and low levels of W_CLK respectively. According to the manual, the above four times are at least 3.5ns. Since the crystal oscillator of the S52 microcontroller is relatively low, there is no problem in meeting the working sequence.
DATA is valid when the rising edge of W_CLK arrives.
The subroutine for writing the frequency control word is as follows:


4 System test
Below is the waveform diagram observed by a 100MHz Tektronix oscilloscope when AD9851 is set to output different frequencies, as shown in Figure 6. From its waveform diagram, it can be seen that the output frequency of DDS is very accurate and stable below 60 MHz, the waveform is relatively perfect, and the spectrum is relatively clean. When the design frequency is 70 MHz, the more serious the waveform distortion is, the more harmonics of the spectrum will increase. The amplitude of the DDS sinusoidal output decreases with increasing frequency, about 1Vpp at the low frequency end and about 200mVpp at the high frequency end. In practical applications, a suitable broadband amplifier should be added.

5 Conclusion
This paper uses the general-purpose AT89S52 microcontroller to complete the design and verification of a sine wave signal generator based on the high-precision DDS chip AD9851.