Application of X25165 chip in 8051 system

The Z25165 chip produced by Xicor Corporation of the United States is an integrated circuit product that integrates the functions of watchdog, voltage monitoring and serial EEPROM. The application of this chip will help simplify the structure of the single-chip computer system, reduce the cost of the system, reduce the space requirement for the circuit board, and increase the reliability of the system.

1 Chip Introduction

The pin arrangement of X25165 is shown in Figure 1, and the function description of each pin is listed in Table 1.

X25165 uses a simple three-wire bus serial peripheral interface (SPI). All operation codes, byte addresses and written data for chip operations are input from the SI pin. The written data is latched on the rising edge of the serial clock (SCK). The data read from the chip is serially shifted out from the SO pin and output on the falling edge of the serial clock.

The chip's watchdog timer and Vcc voltage monitor both provide independent protection for the microprocessor. When a system failure occurs, as long as the watchdog timer reaches its programmable timeout limit, the RESET pin immediately and automatically generates a high-level reset signal that lasts 200ms. When the power supply voltage Vcc drops below 4.5V, the RESET pin immediately and automatically generates a main-level reset signal and protects until the power supply voltage returns to normal. When the system power is powered on or off, the RESET pin also immediately and automatically generates a high-level reset signal. In this way, the occurrence of system crashes, data miswriting, and misoperation can be effectively prevented.

Table 1 Application of X25165 chip in 8051 system

The X25165 chip has a 2k×8-bit serial EEPROM inside, each byte can be erased and written more than 100,000 times, and the internal data can be saved for more than 100 years. When used, the specified block can be locked by programming to prevent the saved data from being destroyed due to misoperation and other reasons.

2 Working Principle

2.1 Instructions

X25165 has seven instructions (see Table 2). All operations on the chip need to be completed by writing commands to the instruction register. All instructions, addresses, and data are transmitted serially in the form of high-order bits first (MSB).

Table 2 Instruction set

2.2 Status Register

X25165 has an eight-bit status register. The contents of the status register can be read at any time through the RDSR instruction, and certain bits in the status register can be set through the WREN, SFLB, WRSR and other instructions. The format of the status register is as follows:

WIP: is a read-only bit used to indicate whether the chip is busy with an internal non-volatile write operation.

WEL: Write enable, indicating the current state of the write enable latch; [page]

BL1, BL0: Set the block protection address range of EEPROM, see Table 3;

Table 3 Block protection address range

WD0, WD1: Select the watchdog timeout period, see Table 4;

Table 4 Watchdog timer timeout period

FLB: read-only bit, indicating the status of a volatile bit, which can be set and cleared by SFLB and RFLB instructions. This bit is automatically cleared when power is turned on.

WPEN: This is a non-volatile bit that can be programmed using the WRSR instruction. This bit and the WP pin can be used together to programmatically implement hardware write protection (see Table 5). When the WP pin is low and the WPEN bit is set, write operations to all status registers are prohibited.

Table 5 Block Protection Matrix

3 Chip Application

3.1 Hardware interface circuit

In an 8051 single-chip microcomputer system, the chip can be used according to the connection method shown in Figure 2.

3.2 Software Interface Design

According to the connection method in Figure 2, the author has written seven practical application interface programs for your reference.

a. Serial output of the program

The data in accumulator A is serially output to the X25165 chip in the order of the most significant bit first (MSB).

WD-OUTB: MOV R7, #08H; 8 bits of data to be transferred

WD-OUTB1: CLR P1.2; make SCK low

RLC A; shift the output bit into C

MOV P1.1, C; carry bit is shifted into SI

SEIB P1.2; make SCK bit high

DJNZ R7, WD-OUTB1; Determine whether the loop is finished

CLR P1.1; Clear SI

RET

b. Serial input subroutine

Read 1 byte of data serially from X25165 into accumulator A in the order of high bit first (MSB).

WD-INB: MOV R7, #08H; 8 bits of data to be received

WD-INB1: SETB P1.2; generate SCK pulse

CLR P1.2 ;

MOV C, P1.0; S0 moves into carry position C

RLC A; accumulator A with carry bit shifted

DJNZ R7, WD-INB1; Determine whether the loop is finished

RET

c. Read status register subroutine

Used to read the status register contents from X25165, and the read contents are stored in A.

WD-RD-SR: CLR P1.2; make SCK low

CLR P1.3; Chip select CS valid

MOV A, #05H; RDSR instruction sends accumulator A

LCALL WD-OUTB ; Output RDSR instruction

LCALL WD-INB ；Read the status register contents

CLR P1.2; Make SCK low

SETB P1.3; Chip select CS is invalid

RET

d. Write status register subroutine

This subroutine can set the block protection address range and the programmable watchdog timer timeout period. In the subroutine, the chip select signal must be enabled first, and then the write enable latch must be set using the WREN instruction. After the 8-bit instruction is output, the chip select signal must be pulled high to make the command effective. Similarly, the chip select signal must be pulled high after the data output is completed. [page]

WD-WR-SR: CLR P1.2; make SCK low

CLR P1.3; Chip select CS valid

MOV A, #06H; WREN instruction sends accumulator A

LCALL WD-OUTB ; Output WREN instruction

SETB P1.3; Make CS high

CLR P1.3; Chip select CS valid

MOV A, #01H; WRSR instruction sends accumulator A

LCALL WD-OUTB; Output WRSR instruction, set status register

MOV A, #10H; no block protection, timeout period; 800ms

LCALL WD-OUTB ；Output status register content

CLR P1.2; Make SCK low

SETB P1.3; Make CS high

RET ;

e. Read storage unit content subroutine

To read the contents of a specified unit from the serial EEPROM of the X25165, you need to send a READ instruction and a 16-bit address first. The data of the specified address unit will be shifted out from the S0 pin in sequence under the action of the SCK pulse.

WD-RD-DATA: CLR P1.2; make SCK low

CLR P1.3; Chip select CS valid

MOC A, #03H; READ instruction sends accumulator A

LCALL WD-OUTB; output READ instruction

MOV A, DPH; high address is sent to accumulator A

LCALL WD-OUTB ；output high address

MOV A, DPL; low address sent to accumulator A

LCALL WD-OUTB ；output low address

LCALL WD-INB ；Read the data of (DPTR) unit

MOV R4, A; data is sent to R4

LCALL WD-INB ；Read the data of (DPTP+1) unit

MOV R5, A; data is sent to R5

CLR P1.2; Make SCK low

SETB P1.3; Chip select CS is invalid

RET

f. Write storage unit content subroutine

This subroutine writes data to the specified starting address of the EEPROM in the chip. Like the write status register subroutine, the program needs to output the WREN instruction to set the write enable latch. Then, the 16-bit address stored in DPTR and the 16-bit data stored in R5 and R4 are output in the order of high bit first. Finally, the WIP bit of the status register is cyclically checked until the write operation of the core content is completed to ensure that the data is written to the chip safely and reliably.

WD-WR-DATA: CLR P1.2; make SCK low

CLR P1.3; Chip select CS valid

MOV A, #06H; WREN instruction sends accumulator A

LCALL WD-LUTB ; Output WREN instruction

SETB P1.3; Make CS high

CLR P1.3; Chip select CS valid

MOV A, #02H; WRITE instruction sends accumulator A

LCALL WD-OUTB ; Output WRITE instruction

MOV A, DPH; output high 8 bits of address

LCALL WD-OUTB;

MOV A, DPL; output low 8 bits of address

LCALL WD-OUTB;

MOV A, R4; output low 8 bits of data

LCALL WD-OUTB;

MOV A, R5; output high 8 bits of data

LCALL WD-OUTB;

CLR P1.2; Make SCK low

SETB P1.3; Make CS high

WD-WIP-POLL: LCALL WD-RD-SR; Read status register

JB ACC.0, WD-WIP-POLL

; Check WIP position

RET

g. Watchdog timer reset subroutine

As long as the subroutine is executed within the set watchdog timer timeout period and a falling edge is sent to the CS pin of the chip, the watchdog will not generate a reset output signal.

WD-EAT: SETB P1.3;

CLR P1.3; Generate CS falling edge pulse

SETB P1.3 ;

RET

The author used the X25165 chip when designing the wheel diameter axial displacement detector, which simplified the system structure, reduced costs, and improved system reliability. The data saved during use has never been lost, and the results are satisfactory.