Design of PCI Interface of Single Chip Microcomputer Based on CPLD

1 PCI interface design principle

1.1 Introduction to PCI Bus Protocol

Here we only discuss the PCI bus 2.0 protocol. Other protocols are just some extensions based on 2.0. As far as the communication between the microcontroller and the PCI device is concerned, it is of little significance. The PCI bus is a high-performance local bus with an operating frequency of 0 to 33MHz, which can support multiple sets of peripheral devices at the same time. Here, we only care about the communication between the microcontroller and a PCI device, and the microcontroller and CPLD are the master and the other is the PCI slave. The purpose of this is to simplify the problem and reduce the system cost.

Although there are many signal lines on the PCI bus, not every signal needs to be used. In fact, PCI devices do not support all signal lines. For example, the error reporting signals PERR and SERR are not supported in the network card. We can choose to support some of the signal lines according to specific applications, and some signal lines can be directly connected to the power supply or ground. The following is a brief introduction to the functions of common signal lines.

AD[31～0]: Address data multiplexing signal. The first cycle when FRAME is valid is the address, and when IRDY and TRDY are valid at the same time, it is the data.

C/BE[3～0]: Bus command and byte enable control signal. The bus command is transmitted in the address period; the byte enable control signal is transmitted in the data period, indicating which bytes in AD[31～0] are valid data. Table 1 is a description of the bus command encoding.

All data transfer on the PCI bus is basically controlled by the following three signal lines.

FRAME: frame cycle signal. Driven by the master device, it indicates the start and duration of an access. When FRAME is valid (0 is valid, the same below), it means that data transmission is in progress. When it is invalid, it is the last cycle of data transmission.

IRD: Master ready signal. Driven by the master device, it indicates that the master device is ready for data transmission.

TRDY: Slave ready signal. Driven by the slave master, it indicates that the slave is ready for data transmission. Data transmission will actually occur when IRDY and TRDY are both valid.

In addition, there is an IDSEL signal used as a chip select signal during configuration space read and write. For the case of only one PCI slave device, it can always be connected to a high level. The IDSEL signal is driven by the slave device, indicating that the device has become the currently accessed slave device and can be ignored.

When performing read and write operations on the PCI bus, among the various signals on the PCI bus, except for RST, IRQ, IRQC, and IRQ, only the falling edge signal of the clock will change, while the rising edge signal of the clock must remain stable.

1.2 CPLD Design Planning

Considering the processing power and system cost of the microcontroller and CPLD, the following plan does not support the linear burst transmission of the PCI bus, which requires several consecutive data cycles, but only supports the read and write method of one address cycle plus one data cycle. For most applications, this method is sufficient. There are 13 8-bit registers in the CPLD to store the data required for a PCI bus read and write, among which pci_address0~pci_address3 is the address data during read and write; pcidatas0~pci_datas3 is the data to be written to the PCI device; pci_cbe[3~0] stores the bus command during the address cycle of [NextPage] This article is related to DataSheet: MAX7000 EPM7128, PCI_cbe[7~4] stores the byte enable command during the data cycle; pci_data0~pci_data3 stores the data returned from the PCI device; pci_request is the PCI bus read and write operation status register, which is used to return some information to the microcontroller. When the MCU writes a byte to the pci_cbe register, it resets the state machine in the CPLD, triggering the CPLD to perform read and write operations on the PCI bus; the MCU queries the pci_request register to learn that the read and write operations are completed, and then reads the data returned by the PCI device from the pci_data register.

The state transition diagram of the state machine in CPLD is shown in Figure 3. Each state corresponds to an output of FRAME and IRD signals, while other input and output signal lines can be determined by these two signal lines and the value of pci_cbe and the state of TRDY. When FRAME is valid, AD[31~0] is driven by pci_address, and C/BE[3~0] is driven by the lower 4 bits of pci_cbe; when IRDY is valid, C/BE[3~0] depends on the bus command, either driven by the upper 4 bits of pci_cbe or set to high impedance, and AD[31~0] is set to high impedance when pci_cbe[0] is "0" (PCI read command), and is driven by pci_datas when pci_cbe[0] is "1" (PCI read command). On the other hand, once the TRDY signal line becomes low, the data on the AD[31~0] line is sent to the pci_data register, and the data on the C/BE[3~0] line is sent to the lower 4 bits of the pci_request register.

Considering that under abnormal circumstances, the PCI device will not respond to the PCI bus, that is, TRDY will not be valid, in order to prevent the state machine from falling into a stalemate in state S2, a shift counter mycounter is added. When the IRD signal is valid, the counter starts counting. After the count overflows, regardless of whether the PCI bus operation is completed, the state machine will transfer from state S2 to state S3, that is, the PCI bus operation ends. When TRDY is valid, mycounter.cout will be set immediately.

To check whether the PCI bus operation is completed correctly, you can check whether the highest bit of pci_request is "1", and the values ​​of IRDY and FRAME can be checked by checking the 4th and 5th bits of pci_request respectively. These two bits reflect the state of the PCI bus operation. When both bits are "1", it can be considered that the PCI bus operation has been completed. In practice, if the speed of the microcontroller is not fast enough, it can be considered that the PCI bus operation is always completed immediately. The implementation of these bits can refer to the source code.

2 PCI design interface implementation

2.1 CPLD ABEL HDL Programming

We designed a program for 8-bit single-chip microcomputer to control PCI Ethernet card, and selected ALTERA's MAX7000 series CPLD device. According to the characteristics of Ethernet card, the logic was simplified again, and the final program will be adapted to EPM7128 chip and tested in practice.

The Ethernet card only supports read and write operations on the configuration space and I/O space, and the addresses of these two spaces can be set within 0xFF, so only one pci_address0 register can be used, and other addresses can be directly set to "0"; if there is further restriction, only one byte of data is written to the network card each time, then only one pci_datas0 register can be used, and other values ​​can be set to the same as the pci_datas0 register during specific operations.

The following is the main source code of ABEL HDL. Among them, 16dmux is a 4-16 bit decoder, used for address decoding and gating registers in CPLD; 8dffe is an 8-bit DFFE; abelcounter is an 8-bit shift counter; mylatch8 and mylatch1 are 8-bit and 1-bit latches respectively, and mylatchc is a 1-bit latch with clear function; other variables starting with "my" are tri-state buffers, variables starting with "out" are tri-state nodes, and variables starting with "e" are ordinary nodes. These are no longer declared in the program. [page]

SUBDESIGN abelpci

（

P2[7..3] : INPUT;

READ0 : INPUT

WRITE0 : INPUT;

P0[7..0] : BIDIR;

CLK : INPUT;

TRDY0 : INPUT;

AD[31..] : BIDIR;

CBE[3..0] : BIDIR;

IRDY0 : OUTPUT;

FRAME0 : OUTPUT;

)

VARIABLE

decoder : 16dmux;

mycounter : abelcounter;

pci_c[NextPage]DataSheet related to this article:MAX7000 EPM7128
be: 8DFFE;

PCI_address0 : 8DFFE;

pci_datas0 : 8DFFE;

pci_request[6..0] : mylatch1;

pci_request7 : mylatchc;

pci_data0 : mylatch8;

pci_data1 : mylatch8;

pci_data2 : mylatch8;

pci_data3 : mylatch8;

ss: MACHINE OF BITS (FRAME0,IRDY0)

WITH STATES(s0 = B"11",

s1=B"01");

s2=B"10";

S3=B"11");

BEGIN

decoder.(d,c,b,a)=P2[6..3];

enareg[]=decoder.q[];

pci_che.ena=enareg[0]&p2[7];

pci_cbe.d[]=p0[];

pci_cbe.clk=!WRITE0;

pci_address0.ena=enareg[1]&p2[7]l

pci_address0.d[]=P0[];

pci_datas0.ena=enareg[9]&P2[7];

pci_datas0.d[]=P0[];

pci_datas0.clk=!WRITE0;

pci_data0.gate=!TRDY0;

pci_data0.data[]=AD[7..0];

pci_data1.gate=!TRDY0;

pci_data1.data[]=AD[15..8];

pci_data2.gate=!TRDY0;

pci_data2.data[]=AD[23..16];

pci_data3.gate=!TRDY0;

pci_data3.data[]=AD[31..24];

pci_request[3..0].gate=!TRDY0;

pci_request7.gate=!TRDY0;

pci_request7.aclr=P2[7]&!WRITE0;

pci_request[3..0].data=CBE[];

pci_request[4].data=IRDY0;

pci_request[5].data=FRAME0;

pci_request[6].data=Vcc;

pci_request7.data=Vcc;

eread=P2[7]&!READ0 & WRITE0;

my_P0_data0[].in=pci_data0.q[];

my_P0_data0[].oe=enareg[5]&eread;

my_P0_data1[].in=pci_data1.q[];

my_P0_data1[].oe=enareg[6]&eread;

my_P0_data2[].in=pci_data2.q[];

my_P0_data2[].oe=enareg[7]&eread;

my_P0_data3[].in=pci_data3.q[];

my_P0_data3[].oe=enareg[8]&eread;

my_P0_request[6..0].in=pci_request[6..0].q;

my_P0_request[7].in=pci_request7.q;

my_P0_request[].oe=enareg[13]&eread;

out_P0[]=my_P0_data0[];

out_P0[]=my_P0_data1[];

out_P0[]=my_P0_data2[];

out_P0[]=my_P0_data3[];

out_P0[]=my_P0_request[];

P0[]=out_P0[];

enclr=enareg[0]&P2[7]&!WRITE0;

mycounter.clock=CLK;

mycounter.cnt_en=!IRDY0;

mycounter.aclr=!FRAME0;

mycounter.sset=!TRDY0;

ss.clk=!CLK;

ss.reset=enclr;

ss.ena=Vcc;

CASE ss IS

WHEN s0 => ​​ss="s1";

WHEN s1 => ss="s2";

WHEN s2 => IF mycounter.cout THEN ss =s3;ELSE ss="s2";

END IF;

WHENf s3 => ss="s3";

END CASE;

my_AD_address[7..0].in=in=pci_[NextPage]DataSheet related to this article:MAX7000 EPM7128
address0;

my_AD_address[31..8].in=GND;

my_AD_address[31..0].oe=!FRAME0;

my_CBE_c[].in=PCI_cbe.d[3..0];[page]

my_CBE_c[].oe=!FRAME0;

my_AD_data[31..0].in=pci_datas0.q[8..1];

my_AD_data[31..0].oe=pci_cbe_[0]&FRAME0;

my_CBE_be[].in=pci_cbe.d[7..4];

my_CBE_be[].oe=FRAME0;

out_AD[]=my_AD_address[];

out_AD[]=my_AD_data[];

AD[]=out_AD[];

out_CBE[]=my_CBE_c[];

out_CBE[]=my_CBE_be[];

CBE[]=out_CBE[];

END;

2.2 MCU PCI reading and writing C language programming

&nb

sp; With the help of CPLD, it becomes quite simple for the microcontroller to read and write PCI devices. First, declare the pci_cbe and other registers as external memory variables and specify the address according to the design of CPLD. Then, pass appropriate parameters to the following two read and write sub-functions to complete the read and write operations of the PCI device configuration space, I/O space, and memory space. The return data from the PCI device is stored in the global variable savedata.

In fact, when writing to a PCI device, you can also get the return data from pci_data. This data must be equal to the data written to the PCI device. For the reason, see the ABEL HDL design section. This can be used to perform error checking and fault judgment, depending on the specific application.

bdate unigned char request;

sbit IRDY0=request^4;

sbit FRAME0=request^5;

sbit VALID="request"^7;

void readpci(unsigned char addr,unsigned char cbe){

pci_address0=addr;

pci_cbe=cbe;

request=pci_request;

while(!IRDY0 & FRAME0)) request="pci"_request;

savedata0=pci_data0;

savedata1=pci_data1;

savedata2=pci_data2;

savedata3=pci_data3;

if(!VALID)printf("Data read is invalid! ");

}

void writepci(uchar addr,uchar value0,uchar cbe){

data uchar temp;

pci_address0=addr;

pci_datas0=value0;

pci_cbe=cbe;

request=pci_request;

while(!(IRDY0 & FRAME0)) request="pci"_request;

if(!VALID)printf("Data write is invalid!");

}[NextPage]DataSheet related to this article: MAX7000 EPM7128
bus command during address cycle, PCI_cbe[7～4] stores byte enable command during data cycle; pci_data0～pci_data3 stores data returned from PCI device; pci_request is PCI bus read and write operation status register, used to return some information to MCU. When MCU writes a byte to pci_cbe register, it resets the state machine in CPLD, triggering CPLD to perform PCI bus read and write operation; MCU knows the read and write operation is completed by querying pci_request register, and then reads the data returned by PCI device from pci_data register.

The state transition diagram of the state machine in CPLD is shown in Figure 3. Each state corresponds to an output of FRAME and IRD signals, while other input and output signal lines can be determined by these two signal lines and the value of pci_cbe and the state of TRDY. When FRAME is valid, AD[31~0] is driven by pci_address, and C/BE[3~0] is driven by the lower 4 bits of pci_cbe; when IRDY is valid, C/BE[3~0] depends on the bus command, either driven by the upper 4 bits of pci_cbe or set to high impedance, and AD[31~0] is set to high impedance when pci_cbe[0] is "0" (PCI read command), and is driven by pci_datas when pci_cbe[0] is "1" (PCI read command). On the other hand, once the TRDY signal line becomes low, the data on the AD[31~0] line is sent to the pci_data register, and the data on the C/BE[3~0] line is sent to the lower 4 bits of the pci_request register.

Considering that under abnormal circumstances, the PCI device will not respond to the PCI bus, that is, TRDY will not be valid, in order to prevent the state machine from falling into a stalemate in state S2, a shift counter mycounter is added. When the IRD signal is valid, the counter starts counting. After the count overflows, regardless of whether the PCI bus operation is completed, the state machine will transfer from state S2 to state S3, that is, the PCI bus operation ends. When TRDY is valid, mycounter.cout will be set immediately.

To check whether the PCI bus operation is completed correctly, you can check whether the highest bit of pci_request is "1", and the values ​​of IRDY and FRAME can be checked by checking the 4th and 5th bits of pci_request respectively. These two bits reflect the state of the PCI bus operation. When both bits are "1", it can be considered that the PCI bus operation has been completed. In practice, if the speed of the microcontroller is not fast enough, it can be considered that the PCI bus operation is always completed immediately. The implementation of these bits can refer to the source code.

2 PCI design interface implementation

2.1 CPLD ABEL HDL Programming

We designed a program for 8-bit single-chip microcomputer to control PCI Ethernet card, and selected ALTERA's MAX7000 series CPLD device. According to the characteristics of Ethernet card, the logic was simplified again, and the final program will be adapted to EPM7128 chip and tested in practice.

The Ethernet card only supports read and write operations on the configuration space and I/O space, and the addresses of these two spaces can be set within 0xFF, so only one pci_address0 register can be used, and other addresses can be directly set to "0"; if there is further restriction, only one byte of data is written to the network card each time, then only one pci_datas0 register can be used, and other values ​​can be set to the same as the pci_datas0 register during specific operations.

The following is the main source code of ABEL HDL. Among them, 16dmux is a 4-16 bit decoder, used for address decoding and gating registers in CPLD; 8dffe is an 8-bit DFFE; abelcounter is an 8-bit shift counter; mylatch8 and mylatch1 are 8-bit and 1-bit latches respectively, and mylatchc is a 1-bit latch with clear function; other variables starting with "my" are tri-state buffers, variables starting with "out" are tri-state nodes, and variables starting with "e" are ordinary nodes. These are no longer declared in the program.

SUBDESIGN abelpci

（

P2[7..3] : INPUT;

READ0 : INPUT

WRITE0 : INPUT;

P0[7..0] : BIDIR;

CLK : INPUT;

TRDY0 : INPUT;

AD[31..] : BIDIR;

CBE[3..0] : BIDIR;

IRDY0 : OUTPUT;

FRAME0 : OUTPUT;

)

VARIABLE

decoder : 16dmux;

mycounter : abelcounter;

pci_c