Application of I2C Real-time Clock/Calendar Chip in 8051 System

1 PCF8563 Introduction

PCF8563 is a low-power CMOS real-time clock/calendar chip produced by PHILIPS. The maximum bus speed of the chip is 400kbits/s. After each read and write of data, its embedded word address register will automatically generate an increment. PCF8563 can be widely used in mobile phones, portable instruments, fax machines, battery power supplies and other products.

The pin arrangement of PCF8563 is shown in Figure 1, and the function description of each pin is listed in Table 1.

The PCF8563 has 16 8-bit registers, including: an address register with auto-increment, a built-in 32.768kHz oscillator (with an internal integrated capacitor), a frequency divider (for providing the source clock for the real-time clock RTC), a programmable clock output, a timer, an alarm, a power-off detector and a 400kHz I2C bus interface.

All 16 registers are designed as addressable 8-bit parallel registers, but not all bits are used. When an RTC register is read, the contents of all counters will be latched, thus, in the transmission condition, the wrong reading of the clock/calendar chip can be prohibited.

Table 2 and Table 3 list the registers and their corresponding memory addresses and functions, and also list their BCD format codes. In the table, "——" indicates an invalid bit, and "0" indicates that this bit should be set to logic. The century bit in Table 3 C=0 specifies the century number as 20XX, and C=1 specifies the century number as 19XX. The century bit will only change when the 99 in the year register changes to 00.

Table 1 Pin Description of PCF8563

2 I2C bus

2.1 I2C Bus Characteristics

The I2C bus uses two lines (SDA and SCL) to transfer information between chips and modules. SDA is the serial data line and SCL is the serial clock line. These two lines must be connected to the positive power supply with a pull-up resistor. The data can only be transmitted when the bus is not busy. The system configuration of the I2C bus is shown in Figure 2. The device that generates the signal is the transmitter, the device that receives the signal is the receiver, the device that controls the signal is the master device, and the device that receives the controlled signal is the slave device.

Table 2 Register Overview

Table 3 Overview of BCD format registers

2.2 Start and Stop Conditions

When the bus is not busy, the data line and the clock line remain at a high level. When the data line (SDA) is at a falling edge and the clock line (SCL) is at a high level, it is a start condition (S); when the data line is at a rising edge and the clock line is at a high level, it is a stop condition (P), see Figure 3. [page]

2.3 Bit Transfer

Each clock pulse transmits one data bit. The data on the SDA line should remain stable when the clock pulse is high, otherwise it will become a control signal, see Figure 4.

2.4 Flags

There is no limit to the amount of data that the transmitter can send to the receiver between the start and stop conditions. After each 8-bit byte, a flag is added. The transmitter generates a high-level flag, and the master device generates an additional flag clock pulse.

The slave receiver must generate a flag after each byte received, and the master receiver must also generate a flag after each byte received from the slave transmitter. The SDA line should remain low when the flag clock pulse appears (start and hold times should be considered). The transmitter should go low when the last byte is received from the slave device, causing the receiver to generate a flag, and the master device can then generate a stop condition. See Figure 5.

2.5 I2C Bus Protocol

Before using the I2C bus to transfer data, the receiving device should first indicate the address. After the I2C bus is started, this address is transmitted together with the first transmission byte. PCF8563 can be used as a slave receiver or a slave transmitter. At this time, the clock signal line SCL can only be an input signal line, and the data signal line SDA is a bidirectional signal line. See Figure 6 for the slave address of PCF8563.

3 Application Overview

Figure 7 shows the specific application circuit diagram of PCF8563. For the adjustment of the quartz chip frequency in the figure, the author provides three feasible methods for reference:

Method 1: Fixed value OSCI capacitor. Calculate the required average capacitance. With this fixed value capacitor, the frequency measured on the CLKOUT pin after power-on should be 32.768kHz. The measured frequency value deviation depends on the quartz crystal itself. The capacitance deviation and the deviation between devices are ±5×10-6 on average. The average deviation can reach 5 minutes/year.

Method 2: OSCI fine-tuning capacitor. You can get higher accuracy by adjusting the frequency of the fine-tuning capacitor oscillator of the OSCI pin. At this time, you can measure the signal frequency on the CLKOUT pin to be 32.768kHz when the power is on.

Method 3: OSCI output: Directly measure the output of the OSCI pin.

4 Program Examples

The following C language source program uses the common I/O port (such as P0.0/P0.4) of the 8051 microcontroller to simulate the operation of the I2C clock/calendar chip of PCF8563, with two states of byte write/read. In the program, the read address of the slave address is 0A3H, and the write address is 0A2H. The data bytes sent are 9, and the initial data sent is in rom_sed[9]. rom_sed[9] defines the current values ​​sent in the registers: control/status register 1 is 0, control/status register 2 is 0, second register is 0, minute register is 55, hour register is 23, day register is 31, week register is 6, month/century register is 0x12, and year register is 0x99 (i.e. 23:55:00 on December 31, 1999). After the program runs for a period of time (5 minutes), it starts to read data from address register 02H, and the data is stored in rom_rec7. It is found that variable rom_rec7 becomes 0:00 on January 1, 2000. If the external transfer circuit has a display, the time can be displayed on the panel.

#include

#define byte unsigned char

sbit scl=0x81; //define serial I/O port

sbit sda=0x80;

idata byte rom_sed[9];

idata byte rom_rec[7];

idata byte j,k;

bit flag,flag1;

void delay(void) //delay subroutine

{data byte i;

for(i=0;i<6;i++);

}

void I_start(void) //Send I2C bus start condition subroutine

{sda=1;

;

scl=1;

delay();

sda=0;

delay();

scl=0;

;

}[page]

void I_stop(void) //I2C bus stop condition subroutine

{sda=0;

;

scl=1;

delay();

sda=1;

delay();

}

bit I_send(byte I_data) //byte data transmission subroutine

{data byte i;

for(i=0,i<8;i++)

{sda-(bit)(I_data&0x80);

I_data=I_data<<1;

;

scl=1;

delay();

scl=0;

}

;;

sda=1; ;; //ready for receiving ACK bit

scl=1; ;; //start receiving ack bit

flag=0;

if(sda= =0)flag=0;

else flag=1; //return(~I_clock());

scl=0;

return(flag);

}

byte I_receive(void) //byte data receiving subroutine

{ data byte i;

byte I_data=0;

sda=1;

for(i=0;i<8;i++)

{ I_data*=2;

;

scl=0;

delay();

scl=1; ;;

if(sda= =1)I_data++;

;;

}

scl=0; ;;;

sda=0;

if(flag1= =0){;;scl=1;delay();scl=0;} //not last receic_byte ACK

else{sda=1; ;;scl=1;delay();scl=0;flag1=0;} //the last receive_byte ~ACK

return(I_data);

}

main() //Main program

{data byte i;

rom_sed[0]=0x00; rom_sed[1]=0x00;

rom_sed[2]=0x00; rom_sed[3]=0x55;

rom_sed[4]=0x23; rom_sed[5]=0x31;

rom_sed[6]=0x06; rom_sed[7]=0x92;

rom_sed[8]=0x99;

for(i=0;i<255;i++)delay();

I_start();

if(～I_send(rom_sed[i]));

else;

}

I_stop();

}

else;

}

else;

start: I_start();

if(~I_send(0xa2)) //pcf_write address

{if(~I_send(0x02)) //pcf_status register address

{I_start();

if(~I_send(0xa3)) //write status register

{for(i=0;i<7;i++)

{if(i= =6)flag1=1;

else flag1=0;

rom_rec[i]=I_receive();

switch(i)

{case 1:rom_rec[i]=rom_rec[i]&0x7f;break;

ease2:

case3:rom_rec[i]=rom_rec[i]&0x3f;break;

case4:rom_rec[i]=rom_rec[i]&0x07;break;

case5:rom_rec[i]=rom_rec[i]&0x9f;brealk;default:break;

}

}

I_stop()

}

}

}

goto start;

}