Using ispLSI to realize the communication between single chip microcomputer and computer

The single-chip microcomputer has a simple structure and is easy to develop. It can meet the needs of various application fields and has been widely used in industrial control and automation devices. It can be used alone, or multiple chips can work together or as a signal preprocessor for a computer. In this case, the communication problem becomes a bottleneck that limits the performance of the system. There are two commonly used communication methods: serial and parallel. The serial method has a simple hardware structure but a low data transmission rate, which is not suitable for the transmission of large quantities of data; the interrupt method is the most commonly used in the parallel method in order to improve CPU efficiency. However, there are also many problems with the interrupt method. In addition to specific interrupt services, protecting and restoring breakpoints and register contents, checking interrupt vectors, etc. also take up a lot of CPU time. If the data is long, the CPU will be interrupted multiple times when transmitting a group of data. The protection and recovery of a large number of breakpoints and registers particularly affect CPU efficiency. In order to solve this problem, this paper proposes a new communication method, called the interrupt query method, and uses the in-system programmable logic device ispLIS1016 to implement the communication interface.

1 Communication principle

The essence of the interrupt query mode is the combination of the interrupt mode and the query mode: the communicating parties enter the data transmission state by the interrupt mode, and then both parties complete the data transmission by using the query mode within the interrupt, until a group of data is transmitted and each party exits the interrupt service.

Based on this approach, the communication interface should have functions such as data latching, state control, and interrupt generation. As shown in Figure 1-1, the interface block diagram, data latching is completed by latch m and latch s, which latch the data sent to the host computer and the single-chip microcomputer respectively; interrupt and status signals are formed by the state controller, including interrupt signals (INTm and INTs), data latch m full (FULLm), latch s full (FULLs), and data transmission completed (ENDm and ENDs) and other states for both parties to query; communication data and various status signals are transmitted through the data bus, and the communication parties read data or read status controlled by their respective address decoders, selected by the data selector; the three-state output of data is realized by the data buffer. We take the example of a computer sending data to a single-chip microcomputer to illustrate the data transmission process: when the computer writes data into latch s, the state controller generates an interrupt request signal INTs and sets the states FULLs=1 and ENDs=0; after the single-chip microcomputer responds to the interrupt, it receives data in a query mode and queries the state information FULLs and ENDs. Each time FULLs=1, a data is read. At the same time, the read signal clears FULLs to 0 through the state controller and generates an interrupt signal INTm; since it is in the sending state, after the computer enters the interrupt, it first checks FULLs, waits for FULLs=0, and then writes data to the data latch s (only using the write signal), sets ENDs and exits the interrupt. After the single-chip microcomputer finds that FULLs=0 but ENDs=1, it stops receiving data and exits the interrupt, and one communication is completed.

It can be seen that when using this method to transmit data, no matter how large the data volume is, the CPU only responds to one interrupt during each data transmission process. Compared with a single interrupt method, it saves the CPU's interrupt response time. For the transmission of large amounts of data, it is not only efficient, but the data volume can be changed arbitrarily, and it is very flexible to use.

2 Implementation of interface functions

As can be seen from the block diagram shown in Figure 1-1, the above interrupt query interface not only needs a data channel with latches and buffers, but also interrupts, state control, address decoding and data selection logic, and the circuit is relatively complex. However, the emergence of programmable logic devices and electronic design automation tools has enabled complex circuits to be implemented on single-chip programmable logic devices, which not only simplifies the design, but also makes the hardware design as easy to modify as software. For the above interrupt query interface, we use LATTICE's in-system programmable logic device is-pLSI1016 to implement its function. In this way, the design of the interface is transformed into the design of its circuit description file, which can use schematic diagrams or HDL hardware description languages. Compared with schematic diagrams, hardware description languages ​​are not only easy to design, read and save, but also easy to simulate and perform logic synthesis, and are more suitable for the description of complex circuits. Therefore, we use ABEL-HDL hardware description language for design.

In the Synario environment, add the ABEL-HDL resource file to the selected device, enter the corresponding module name and file name, and then open the ABEL-HDL language editing window [2].

The key to circuit design using ABEL language lies in the definition of each signal and the corresponding logic description. As far as the above interface is concerned, the address bus, data bus, read, write and interrupt signals are directly connected to the CPU of both communicating parties, and should obviously be defined as pins; while the data latch and each state signal are connected to the data bus through the data selector, so they are nodes, as shown in Table 2-1. Among them, A, D, RD, WR, Q represent the address line, data line, read, write and data latch output signals respectively, and the subscripts m and s represent the host computer and the single-chip microcomputer respectively; the data output is defined as a buffer in the table in order to directly utilize the three-state output function of each I/O pin of ispLSI1016, so as to omit the data buffer in Figure 1-1. In addition, the state signals FULL and END should be registers with asynchronous clear and set functions to store the corresponding state information during the data exchange process, but designing asynchronous control in programmable logic devices is complicated and wastes resources. This paper designs them as basic RS flip-flops, so the corresponding reverse output nodes FUL1 and EN1 are defined.

The logical relationship of each signal in the ABEL language design file can be given in many ways. This design mainly uses registers and RS flip-flops, so it is appropriate to use logic equations. From the above interface principle, it can be seen that both communication parties of this interface need 3 ports: data input/output port, status port and END signal setting port. Assume that the corresponding port addresses of the host computer are 300H, 308H and 310H, and the 3 port addresses of the microcontroller are 8000H, 8010H and 8020H respectively. Comparing the block diagram shown in Figure 1-1 and the working principle of the interface, the ABEL language equation of the circuit can be given according to the functional block. [page]

The data latch is the basis for reliable data transmission. For the host computer, writing data to the 300H unit means writing the data into the latch s. That is to say, the input signal of the latch s is the data bus of the host computer, and the clock is the write signal of the host computer to the 300H unit. The corresponding ABEL language equation can be expressed as:

In order to reduce the off-chip wiring of the system, the input of the latch Qs is defined as the pin (.pin) of the three-state data output in formula (2-1). Under the premise of ensuring the interface function, the connection between the Qs input terminal and the data bus in the is-pLSI1016 chip is realized.

The data selector selects different signals according to the reading of different addresses by both communicating parties, and its ABEL language equation is:

Ds. oe=! RDs & ((ADRs==＾h8000)#(ADRs==＾h8010)); (2-3)

when（ADRs＝＝＾h8000）then Ds＝Qs; else when（ADRs＝＝＾h8010）then Ds＝STs; (2-4)

Where, STs = [FULLs, FULLm, ENDs, ENDm, x, x, x, x, x, x, x, x, x, x, x, x], and the introduction of 12 arbitrary values ​​of x is to match STs with the data bus width. Since the data buffer in Figure 1-1 is omitted, the output of the data selector is the data bus, so its three-state control terminal is the "OR" signal of the microcontroller read data (8000H) and read status (8010H) signals.

The status signal is the guarantee of correct data transmission and the basis for both parties to read and write data. In terms of timing, the setting and clearing of FULLs are triggered by the write and read signals of Qs, that is, FULLs is determined by equations (2-5) and (2-6):

! FULLs＝（!（ADRm＝＝＾h300）#WRm）&FUL1s;（2-5）

! FUL1s＝（!（ADRs＝＝＾h8000）#RDs）&FULLs;（2-6）

Among them, FUL1s is the inverting output terminal of FULLs. The clearing of ENDs and the setting of FULLs are generated at the same time, but its setting must be triggered by the host computer writing the 310H unit, so the ABEL language equation of ENDs is:

! ENDs＝（!（ADRm＝＝＾h310）#WRm）&EN1s;

! EN1s=(!(ADRm==＾h300)#WRm)&ENDs;

Obviously, whether the host computer writes data to Qs or reads data from Qm, INTs should be set, so INTs = FULLs + FULLm, but if FULLm is zero, INTs will always be 1 and no interrupt will be generated. To solve this problem, we write the equation of INTs as:

INTs=FULLs#! (FULLm#ENDm); (2-9)

When ENDm is zero, it is operated according to INTs = FULLs + FULLm. As long as the software controls and ensures that the states of both parties before each communication are: ENDs = ENDm = 1, FULLs = FULLm = 0, correct interruption and communication can be achieved. Obviously, it is not difficult to write the logical relationship of each signal on the host computer side using the same method, and this article will not repeat it.

Through the above design, we have realized data communication between the main computer and multiple 80C196 single-chip computer systems, and placed each 80C196 system in the bus expansion slot of the main computer, so that the entire system not only has fast communication speed, but also has stable and reliable performance and good results.

[References]

［1］ Liu Leshan et al. Principles and Applications of Microcomputer Interface Technology. Huazhong University of Science and Technology Press, 1996.3
［2］ Huang Zhengjin. In-system Programming Technology and Its Application［M］. Southeast University Press, 1997.8