Low power consumption design based on 51 series single chip microcomputer

Introduction
In the design of control terminal systems, when the system requires low overall power consumption, the C8051F series of microcontrollers is the best choice. They have flexible clock hardware, which enables the system to easily switch between high-efficiency operation mode and low-power mode. The intelligent power management mode can switch freely between normal operation and standby state, thereby reducing the energy loss of the entire system; when the operating frequency is lower than 10kHz, the clock loss detector (MCD) can trigger a system reset to ensure safe and reliable system operation.

1 Power consumption of each component of C8051F
When a system has strict requirements on power consumption, you can roughly calculate the power consumption required by the entire system before building the hardware circuit. Since the C8051F series microcontroller is a mixed digital-analog SOC system that can realize most of the functions of the entire design, the power consumption of the entire design system will mainly focus on the energy consumption of the C805IF series microcontroller.

The power consumption of the entire microcontroller system should be composed of four parts: oscillator power consumption, digital device power consumption, analog peripheral power consumption and I/O port power consumption. Oscillator power consumption includes internal oscillator power consumption and external oscillator power consumption. Digital device energy consumption is mainly determined by the CPU's operating mode, operating voltage and system clock frequency. Temperature and digital peripherals have little effect on the power consumption of digital devices. Analog peripheral power consumption mainly includes ADC, voltage reference VREF, temperature sensor, bias generator and internal oscillator. The comparator also has a small amount of energy loss. 1.1 Oscillator power consumption analysis The external oscillator is highly configurable and provides system designers with a variety of options. The time base signal can be obtained from an external CMOS level clock source, a crystal oscillator or ceramic resonator, an RC combination circuit or an external capacitor. Each method has its own advantages. Since the oscillator can be flexibly switched in various ways, power consumption can be reduced by changing the oscillator. For external oscillators, external CMOS clocks, capacitors and RC networks can all provide lower oscillation frequencies. (1) External CMOS clock When operating in external oscillator CMOS clock mode, the external oscillator driver is turned off. The circuit power consumption is very small and can be almost ignored. The time base signal output by XTAL2 can be used as a clock source for the CPU, timer, PCA or other peripheral devices. Note that even if a high-frequency signal is applied to a port, the power consumption is only slightly increased. (2) External crystal oscillator External crystal oscillator provides the most accurate time base, but the power consumption is also higher at the same frequency. The external crystal oscillator depends on the crystal frequency and the oscillator drive circuit (XFCN). (3) External capacitor C mode External capacitor mode provides a low-power clock for the system by connecting a capacitor to XTAL2. This is the least accurate time base method, but it is also the most flexible method. Only one capacitor element can provide 8 different operating frequencies. The highest frequency can reach almost 3000 times the lowest frequency. The oscillation frequency can be changed by changing the XFCN bit in the OSCXCN register, which directly affects the output current. The time base accuracy in the external capacitor mode is mainly determined by the error of the capacitor and the accuracy of the internal current source flowing through XTAL2. (4) External oscillation RC mode The RC mode is very similar to the capacitor mode. The difference is that in the external capacitor mode, the charging current of the capacitor is provided by the internal programmable current source connected to XTAL2, and in the RC mode, the charging and discharging circuit includes an external resistor in addition to the capacitor. The average power consumption of the RC mode oscillation circuit is determined by the average current passing through the resistor. The voltage drop across the resistor is exponentially large, and its waveform can be simplified to a triangular wave to estimate the average value. Generally, designers can achieve the purpose of reducing power consumption by reasonably selecting the clock source. The typical value of the digital power supply current consumed by the internal oscillator is 200μA, and the current used to drive the external oscillator is variable. For an external oscillator source (such as a crystal), the drive current (provided by the analog power supply) is set by software by configuring the XFCN bit of the external oscillator control register OSCXCN. When the drive current is large, the user can use the internal oscillator to reduce power consumption. 1.2 Power consumption analysis of digital devices The energy consumption of digital devices is mainly measured by the size of the CPU current. The power mode of the CPU is a key factor in determining the CPU current size, operating voltage and system clock frequency. Usually, temperature and digital peripherals have only a small impact on the power consumption of digital devices. (1) OPU power management mode The CPU has three operating modes: normal state, idle state and stop state. Usually, the average current value in the idle state is controlled by the internal oscillator. The current value in normal mode minus the current value in idle mode is the operating current value of the CPU for normal operation. When l is written to the IDLE bit, the CPU ends the instruction cycle and enters low power mode until it is awakened by an interrupt or reset. In idle mode, all analog and digital peripherals, memory and internal registers retain their original values. After being awakened, the CPU starts executing from the next instruction of the instruction that sets the idle mode selection bit. When 1 is written to the STOP bit, the CPU enters the stop mode. After the stop mode is set, the current instruction is executed, and the internal oscillator and all digital peripherals stop working. Analog peripherals (such as comparators and external oscillators) retain their current states. In the stop state, the MCU consumes the least current. (2) The impact of OPU operating voltage, frequency and temperature on power consumption Operating voltage: The operating current of the CPU will increase with the increase of the supply voltage. This relationship exists at any operating frequency, especially at high frequency operation. Theoretically, the minimum supply voltage can reach 2.7 V, but because the voltage adjustment itself has an error rate of ±10%, the system supply voltage is usually not lower than 3V. Temperature: Temperature has no effect on the power consumption of the system. Operating frequency: The CPU operating frequency has a major impact on the power consumption of the system. In CMOS digital logic devices, power consumption is proportional to the frequency of the system clock SYSCLK: Power consumption = CV2f Where: C is the load capacitance of CMOS; V is the power supply voltage; f is the frequency of SYSCLK. Therefore, in order to reduce power consumption, the designer must know the maximum SYSCLK frequency and accuracy required for a given system. Some designs may require that the system clock frequency remain constant throughout the entire operating time. In this case, the designer will select the lowest frequency that meets the requirements and use the oscillator configuration that consumes the least power. 1.3 Power consumption analysis of digital peripherals and I/O interfaces The loss of digital peripherals (counters, UART, PCA, SPl) accounts for a very small proportion of the total system power consumption. For example, when the C8051F microcontroller operates at 3.06MHz (internal oscillator divided by 8) and 3V, the operating current of no digital peripheral port exceeds 700μA; after starting the counter as the UARTO data transmission clock, the system operating current will increase by 18μA. Here, the power consumption of the counter and UART is mainly determined by their clock frequency and operating voltage. Using a cross switch to configure the general I/O port to push-pull mode can also affect the power consumption. In the above example, if the cross switch is used to assign the TX end of UARTO to the P0.4 port, configuring the port to push-pull mode will increase the system operating current by another 82μA. The power consumption of the output pin is determined by the frequency of the external circuit connected to the pin. 1.4 Power consumption of analog peripherals The power consumption of analog peripherals is the sum of the power consumption of the ADC, temperature sensor, internal bias voltage generator and internal oscillator. Usually, as long as the ADC, internal oscillator or temperature sensor is activated, the internal bias voltage generator will be automatically enabled, and the operating current of the ADC during conversion is 30% to 50% higher than the operating current when the ADC is not converting. The SAR conversion clock frequency and sampling frequency also affect the power consumption. Since increasing the SAR conversion clock frequency or reducing the sampling rate will shorten the time of each A/D conversion, the system will be idle for more time between conversions, which will greatly reduce the system power consumption.







































2 Considerations for reducing power consumption
To reduce the average power consumption of the system, two aspects need to be considered: first, appropriately adjust the parameters that affect the system operation at all times. Usually, the operating voltage is the key parameter to consider. The operating voltage determines whether the system can be in normal operation. It can be provided by a voltage regulator or a battery. For an energy-saving system, the operating voltage should be minimized to save energy. The second point is to build a reasonable firmware structure to reduce power consumption. Two working modes should be designed for the system: one is an efficient operation mode; the other is a sleep mode with the purpose of reducing power consumption. The design standards of the two modes are different, but the system should be kept in sleep mode most of the time to reduce the total power consumption of the system. The following discusses the design of these two aspects in detail. 2.1 Reduce the operating voltage and reduce the operating current The operating voltage plays a vital role in the total power consumption of the system. For energy-saving systems, the lowest operating voltage should be used while ensuring the safety and reliability of the system. Usually, the voltage regulator has an error rate of ±10%, so when designing the operating voltage, the lowest operating voltage should be 3V, and the output voltage of the voltage regulator is between 2.7V and 3.3V. Batteries can also be used. Lithium batteries are recommended here. Lithium manganese dioxide batteries can output a stable 2.85V voltage without any adjustment, and the battery can be directly connected to the power pin of the device. There is no need to worry about the adverse effect on the system operation when the battery is exhausted, because in the C8051F series microcontrollers, the on-chip power monitor can ensure that the system automatically resets after the battery is exhausted. Since the operating voltage is usually constant, the total power consumption of the system is often reduced by reducing the average current. The average operating current is the amount of charge consumed by the system per unit time. For a system, its total operating time should be divided into two parts-high-efficiency working period and low-power sleep period, as shown in Figure 1. The working current of the high-efficiency working period is relatively large, while the current of the sleep period is very small. The average operating current is the average value of the total charge of the system during these two parts divided by the time. Therefore, if you want to reduce the average current value, there are only two ways to solve it-shorten the time of the high-efficiency working period or reduce the peak current of the high-efficiency working period. Designers should try to design the system from these two aspects to achieve the purpose of reducing total power consumption.

2.2 Design a low-power sleep mode
By designing a low-power sleep mode, the system can be kept in a low-consumption state during the non-working period, thereby achieving the purpose of reducing the operating current of the entire system. The sleep mode can be achieved by setting the power management mode to idle or shutdown state. Usually, the idle mode is set because it is easier to recover. It should be noted that all unnecessary peripherals should be turned off in sleep mode, and the clock of the body sleep mode should be configured as an external oscillator. Because the external oscillator can disable the oscillation of the internal oscillator and can oscillate at a very low clock reference. There are two optional oscillators: 36.728kHz crystal oscillator and single capacitor mode external oscillator.

The external capacitor mode oscillator consumes less power than the crystal oscillator, but is not as accurate as the crystal oscillator. Its advantage is that it can make the frequency of clocked peripherals (such as timers) lower than 10kHz. At the same time, because it only contains 1 capacitor, it can save PCB board space compared to the 2 loading capacitors and 1 resistor structure of the crystal oscillator. If a high-frequency crystal oscillator is used in the design, the loading capacitor can be connected to the XTAL2 pin to be used as an external oscillator, and a lower frequency clock can be provided for the sleep mode in C mode. 2.3 Design an efficient operation mode The design of the efficient operation mode should be based on the standard of shortening the time required to complete the operation as much as possible, so that the system can recover to the sleep mode as soon as possible. The design of the mode includes adjusting the peak value of the operating current and the clock frequency to reduce the total charge during the efficient operation period. Usually, the internal oscillator is used in the efficient operation mode, which is more beneficial to reduce the total power consumption of the system. Taking ADC sampling as an example, the consumption rate of system power consumption in the two designs is compared and analyzed. The on-chip temperature sensor samples at a rate of 10Hz, and the external crystal oscillator of the system is connected between XTAL1 and XTAL2. Timer 2 generates an interrupt every 100ms overflow to wake up the system from idle mode. When the system is activated, the system captures the ADC sampling data and then returns to idle mode until the next interrupt occurs. Since the system is battery-powered, the system should minimize the charge consumed by each A/D sampling. Since the charge is the total amount of current in a period of time, energy can be saved by shortening the sampling time or reducing the peak current during sampling. That is, when capturing ADC sampling data, the system can choose to switch to the 3MHz internal oscillator to use a large current in a short time; or use an external 32kHz crystal oscillator as the system oscillator to make the microcontroller use a smaller current value for a long time. Based on the above analysis, two designs were made. One design uses an external 32.768kHz crystal oscillator as the system clock reference during sampling; the other design switches the oscillator to the internal oscillator during sampling to shorten the A/D conversion time. Both systems are in the same idle mode when not sampling. After the first system is awakened from the idle mode, the system directly starts the ADC device to start sampling. The system does not switch to the internal oscillator, but still uses the original 32kHz crystal oscillator as the system clock reference. After the A/D conversion is completed, the system reads the sampled value, turns off the ADC and re-enters the idle mode. In order to capture the sampled data, the system lasts 1.5ms at the peak operating current of 0.65mA. When the second system is awakened from idle mode, the system starts the internal oscillator and ADC, converts the system clock reference to the internal oscillator 8-division mode, and starts ADC conversion. After the conversion is completed, read the ADC data, then stop the ADC and internal oscillator and return the CPU to idle mode. In order to capture the ADC sampling data, the system lasts 400μs at the peak operating current of 2.2 mA. Using the formula:

The calculation shows that the average current of the first design system is 15μA, while the average operating current of the second design system is 14μA. When powered by a 3V lithium battery, the battery life of the first design is 4000h, while the battery life of the second design is 42000h.

From this example, it can be seen that when the system is working efficiently, increasing the system clock frequency can reduce the average operating current of the system, thereby reducing the total power consumption of the system.