Realizing LIN Nodes Using Single Chip Microcomputer

1.1 Introduction

LIN is the automotive communication protocol standard in low-cost networks. LIN (Local Interconnect Network) is a low-cost automotive network that complements the existing various automotive networks in terms of functionality. LIN will be the starting factor for the use of automotive hierarchical networks in cars due to its ability to improve quality and reduce costs. The standardization of LIN will simplify various existing multi-point solutions and will reduce development, production, service and logistics costs in the field of automotive electronics.

The LIN standard includes transmission protocol specifications, transmission media specifications, development tool interface specifications, and interfaces for software programming. LIN ensures the interoperability of network nodes in hardware and software and has predictable EMC functions.

1.2 Chip Introduction

The SPMC75 series MCU is designed and developed by Sunplus Technology Co., Ltd.

The high-performance 16-bit general-purpose MCU has strong anti-interference performance, rich and easy-to-use resources and excellent structure, especially the enhanced timing counter and PWM output functions. The SPMC75 series MCU uses the Lingyang u'nSP core, which is an efficient 16-bit CISC core. It supports high-performance operations such as multiplication, multiplication accumulation, 32/16-bit division, FIR, etc.; it supports two interrupt modes. It can easily generate various motor drive waveforms such as SPWM waves and space vector PWM (SVPWM).

In addition to the high-performance CPU, the SPMC75 series MCU also integrates a variety of functional modules: multi-function I/O port, synchronous and asynchronous serial port, high-performance ADC, ordinary timer counter, multi-function capture comparison module, BLDC motor drive dedicated position detection interface, two-phase incremental encoder interface, PWM generator that can generate various motor drive waveforms, etc. At the same time, the SPMC75 series microcontroller integrates 32K Words of Flash and 2K Words of SRAM. With these hardware support, the SPMC75 series microcontroller can complete complex applications such as household electric variable frequency drive, standard industrial variable frequency drive, multi-ring servo drive system, etc.

TJA1020 (Philips) is the interface between the LIN master/slave protocol controller and the LIN (Local Interconnect Network) physical bus, and is mainly used as a secondary network in vehicles. The baud rate used can be from 2.4 to 20Kbits/s. TJA1020 supports two operating modes: normal slope and low slope, and can switch between normal slope mode and low slope mode. TJA1020 also supports sleep mode to reduce system power consumption.

1.3 Introduction to LIN Bus

LIN (Local Interconnect Network) Bus is a serial communication bus that effectively supports the control of distributed mechanical and electronic nodes in automotive applications. Its scope of application is a multi-point bus with a single master node and a group of slave nodes. Its system structure is shown in Figure 1-1. The main features of the LIN Bus system are:

■ Single-master multi-slave organization (i.e. no bus arbitration), flexible configuration;
■ Low-cost hardware based on ordinary UART/SCI interface to implement low-cost software protocol;
■ Multi-point broadcast reception with time synchronization, slave nodes do not need quartz or ceramic resonators, and can achieve self-synchronization;
■ Guaranteed signal transmission delay time. Optional message frame length: 2, 4 and 8 bytes;
■ Data checksum security and error detection, automatic detection of faulty nodes in the network;
■ Use of semiconductor components with minimum cost (small patch, single-chip system).
■ Speed ​​up to 20kbit/s;

Figure 1-1 LIN Bus system structure

1.4 Implementation of LIN protocol on SPMC75F2313A

LIN Bus is a simple single bus system with a relatively simple software protocol stack. A LIN network consists of a host node and more than one slave node. All nodes include slave service programs to send and receive data, and only one node includes a host service program. The host program is mainly used to send synchronization intervals, synchronization fields, and ID fields (can also be commands) to control and coordinate the orderly communication of each node.

1.5 System Design

The system circuit principle block diagram is shown in Error! Reference source not found. The circuit consists of two parts: MCU control core circuit and LIN interface.

The MCU control core circuit is mainly implemented by SPMC75F2313A, which mainly completes the implementation of LIN protocol and the control of the entire system. SPMC75F2313A integrates the necessary hardware to realize LIN bus nodes, including UART, capture input and sufficient timers. In particular, its capture input function provides great convenience for LIN frame header recognition, frame synchronization and baud rate measurement.

The LIN interface part is mainly composed of the LIN physical layer interface chip TJA1020, which mainly completes the mutual conversion between the MCU communication signal and the LIN physical bus signal, and provides an interface between the MCU and the LIN physical bus.

Figure 1-8 Hardware schematic diagram

1.6 Conclusion

The newly launched SPMC75 by Sunplus Technology is a series of powerful industrial-grade MCUs with strong anti-interference capabilities. It integrates high-performance ADC, enhanced timer counter and other functional components, and powerful capture comparison function and PWM generation function, which makes it have outstanding performance in communication fields such as LIN, RF Mode, IrA, etc. SPMC75 series MCU can be used to easily form various simple and efficient communication systems.

1.4.1 LIN information Transmission

LIN information is transmitted in the form of messages. Message transmission is formed and controlled by the format of the message frame. The message frame transmits synchronization and identifier information from the host task to the slave task, and transmits the information of a slave task to all other slave tasks. The host task is located inside the host node, and it is responsible for the schedule of the message and sending the message header (HEADER). The slave task is located in all (i.e. host and slave) nodes, and one of them (host node or slave node) sends the response (RESPONSE) of the message.

As shown in Figure 1-2, a message frame consists of a message header sent by a host node and a response sent by a host or slave node. The message header of the message frame includes a synchronization interval field (SYNCH BREAK FIELD), a synchronization field (SYNCH FIELD) and an identifier field. The response (RESPONSE) of the message frame consists of 3 to 9 byte fields: 2, 4 or 8 bytes of data field (DATA FIELD) and a checksum field (CHECKSUM FIELD). The byte fields are separated by the inter-byte space, and the message header and response of the message frame are separated by an intra-frame response space. The minimum inter-byte space and intra-frame response space are 0, and the maximum length of these spaces is determined by the maximum length of the message frame TFRAME_MAX.

Figure 1-2 LIN message frame

1.4.2 LIN Information Transmission Process

Figure 1-3 shows the data transmission from the LIN slave to the host. The entire process is coordinated by the host.

Figure 1-3 Data transmission from slave to master

Figure 1-4 shows how a LIN host sends data to two or more slaves. The entire process is coordinated by the host.

Figure 1-4 The host sends data to two or more slaves

Figure 1-5 shows the data transmission between slaves. The whole process is coordinated by the host.

Figure 1-5 Data transmission between slaves

1.4.3 LIN physical layer control

■ SYNCHRONISATION BREAK detection

In order to clearly identify the start of a message frame, the first field of a message frame is a synchronization break. The synchronization break field (SYNCH BREAK FIELD) is sent by the master task and synchronizes all slave tasks with the bus clock signal. The synchronization break field has two different parts as shown in Figure 1-6. The first part consists of a dominant bus level that lasts for TSYNBRK or longer (that is, the minimum is TSYNBRK but does not need to be very strict). The second part is followed by a recessive level that lasts at least TSYNDEL time, which serves as a synchronization delimiter. The second field allows the detection of the start bit of the next synchronization field (SYNCH FIELD). The maximum break and delimiter times are not precisely defined, but must fit within the overall time budget of the entire message header THEADER_MAX, which is defined in Table 1-1.

Figure 1-6 Synchronous interval field

Table 1-1 Message timing

The dominant level length of the sync break field is at least TSYNBRK (can be longer), which is measured in terms of the master bit timing. The minimum value should be based on the threshold required by the minimum local clock frequency specified by the connected slave node.

On the SPMC75F2313A, each time measurement in the synchronization interval is achieved through the capture input. The capture input of the SPMC75F2313A can easily measure TSYNBRK and TSYNDEL, and synchronize with the falling edge of TSYNDEL after the detection is completed.

■ Baud rate measurement

The baud rate measurement is performed on the LIN bus's SYNCH FIELD. The SYNCH FIELD contains the clock synchronization information. The format of the SYNCH FIELD is shown in Figure 1-7. It is achieved by sending "0x55" to the UART, which is reflected in 5 falling edges in the 8-bit timing (i.e., the edge from "hidden" to "dominant"). The capture input function of the SPMC75F2313A can be used to easily measure the time interval between two adjacent falling edges, and the baud rate can be calculated using this time interval.

Figure 1-7 Synchronous field diagram