1 Introduction
ATmegal62 is a low-power CMOS 8-bit microcontroller based on AVR RISC launched by ATMEL. AT-megal62 can achieve a performance close to 1 MIPS/MHz by executing one instruction in one clock cycle, allowing designers to strike a balance between power consumption and execution speed. The AVR core connects 32 general-purpose working registers and a rich instruction set. All working registers are directly connected to the ALU arithmetic logic unit, allowing a single instruction to be executed in one clock cycle and accessing two independent registers at the same time. This structure improves code efficiency and enables AVR to achieve nearly 10 times higher performance than ordinary CISC microcontrollers. This paper uses ATmegal62 to develop three systems: keyboard-LCD display, two-phase DC brushless motor without position sensor, and data acquisition and transmission realized by asynchronous serial communication port. Experiments have shown that these systems developed using ATmegal62 have reliable performance, low cost, flexible software design, and rich hardware interface functions, creating good conditions for future system upgrades.

2 Structure and Features of ATmegal62
ATmegal62 has 35 programmable I/O lines, with various packages such as 40-pin PDIP, 44-pin TQFP and 44-pin MLF. There are 4 8-bit bidirectional I/O ports A, B, C, D, and a 3-bit bidirectional I/OE port with internal pull-up resistor.
Each port has 3 corresponding I/O port registers, namely data register PORTx, direction register DDRx and input pin register PINx. When DDxn is written to 0, the corresponding Pxn is configured as an input pin. When PORTxn is set to 1, the internal pull-up resistor configured for the pin is valid. When DDxn is 1, the corresponding Pxn is configured as an output pin, and the data in POPTxn is the output level of the external pin, that is, 1, the port pin is forced to be driven high, and the output is high level (output current); when PORTxn is cleared, the port pin is forced to be pulled low, and the output is low level (sink current). During the reset process, even if the system clock has not started, the port is a three-state port. It can also be used as an address/data multiplexing port to provide many special interface functions of ATmegal62. Port C provides the function of JTAG interface. When the JTAG interface is enabled, the internal pull-up resistors of pins PC7 (TDI), PC5 (TMS) and PC4 (TCK) are always in effective mode (including reset).
ATmegal62 has the following features: 16 KB of in-circuit programmable Flash with read and write capabilities; 512B EEPROM; 1 KBSRAM memory; 35 general-purpose I/O ports; 1 external memory interface; 32 general-purpose working registers; 1 JTAG interface with boundary scan function; support online compilation, programming and simulation debugging; support programming of Flash, EEPROM, chip fuse bits and confidentiality lock bits; 4 flexible timers/counters with compare mode, 2 8-bit timers/counters with compare mode with prescaler, 2 16-bit timers/counters with compare, capture and capture modes with prescaler, real-time counter with independent oscillator; 6 PWM channels; internal and external interrupt sources; power-on reset and programmable voltage detection circuit; internal calibrable RC oscillator; 2 programmable UART interfaces; programmable watchdog timer with internal clock; SPI serial interface; BOOT area has independent encryption bit, which can be programmed in system through the on-chip boot program, and is truly readable during write operation; fully static operation; on-chip hardware multiplier with execution time of 2 clock cycles; 5 power saving modes selectable by software.
ATmegal62 uses ATMEL's high-density non-volatile memory technology. The on-chip Flash can be programmed and self-programmed through the SPI interface + programmer, or through the JTAG interface, or using the self-boot BOOT program. Using the self-boot BOOT program, the device can download the application program through any hardware serial communication interface during operation and write it to the application program area (IAP) of the Flash. When updating the application program area code of the Flash, the self-boot program in the BOOT area of ​​the Flash will continue to execute, realizing the function of simultaneous reading and writing. Since the enhanced RISC 8-bit CPU and the Flash memory for in-system programming and in-application programming are integrated into one chip, ATmegal62 becomes a powerful single-chip microcomputer, providing a flexible and low-cost solution for multiple embedded control applications.

ATmegal62 is a high-end microcontroller in the AVR series. It is a very complex microcontroller. Its I/O addresses replace the 64 I/O addresses reserved in the AVR instruction set. To ensure backward compatibility with ATmegal61, the locations of all I/O on ATmegal62 are the same as ATmegal61. Many additional I/O addresses are added to an extended external I/O space of $60$FF. These addresses can only be accessed with LD/LDS/LDD and ST/STS/STD instructions, but not with IN and OUT instructions. For ATmegal61, there is a problem of relocation of internal RAM space. Similarly, if the code uses absolute addresses, the added interrupt vectors are also a problem. To solve these problems, the compatibility mode of AT- megal61 can be selected by programming fuse M161C. In this mode, there are no such differences between ATmegal62 and ATmegal61.
(1) Address space 0x0060-0x00FF is used to expand external I/0 instead of internal SRAM;
(2) Address space 0x0100-0x04FF is used as internal SRAM, so the external memory starts at address 0x500 (ATmegal61's external memory starts at address 0x460);
(3) UART has an input buffer that allows one more byte of data to be received before the data overflow flag (DOR) is set to 1;
(4) Extended interrupt vectors are removed.
ATmegal62 is fully pin-compatible with ATmegal61 and can replace ATmegal61. However, the address fuse bits and electrical characteristics of the two devices are different. In ATmegal61 compatibility mode, AT-megal62 does not have the following features:
(1) USART FIFO operation;
(2) Timer/Counter 3;
(3) Access to the system clock prescaler;
(4) Pin interrupts for Port A and Port C;
(5) Specific timing when changing the WDT prescaler setting through software;
(6) M161C fuses remap the interrupt vectors to be the same as ATmegal61.

4 Engineering Application of ATmegal62
4.1 Design of ATmegal62, Keyboard and LCD Display
The keyboard is an indispensable input tool for various CPUs. It can be used to input programs and data, thus realizing human-computer dialogue. Liquid crystal display (LCD) is increasingly widely used due to its low power consumption, small size, rich display content, and ultra-thin and lightweight advantages. DM12864 is a graphic dot matrix LCD display. It adopts the dynamic drive principle and consists of a row driver controller and a column driver to form a 128 (column) × 64 (row) full dot matrix LCD display, which can display graphics and Chinese characters. It can be directly connected to the single-chip microcomputer and has special instructions, which can easily realize functions such as screen scrolling. Figure 1 shows a keyboard-LCD display application system developed using ATmegal62. The keyboard keys are arranged in a 3x4 matrix form. The I/O port lines PB1-PB3 are input (set to 0) and serve as the column scan lines of the keyboard; PB4-PB7 are output (set to 1) and serve as the row scan lines of the keyboard, with pull-up resistors. When it is determined that a key is pressed, the key jitter is removed by delay, and the position of the closed key is determined again. If a key is indeed pressed, the key value is calculated and returned. The operating voltage of the LCD is +5V±10%; PC2 is used as the register data/instruction selection signal D/I. When D/I is 1, data is displayed, and when D/I is 0, instruction code; PC3 is used as the read/write operation selection signal R/W. When R/W is 1, data or instructions are read, and when R/W is 0, data or instructions are written; PC0 and PCI are used as the left and right half-screen chip select signals CS1 and CS2 of the LCD respectively; the reset signal RST is connected to PEl, and the high level resets DM12864; PE0 is used as the enable signal EN of the LCD; PA is used as the parallel data bus DB, which is used to transmit data between the two. Before reading/writing display data to the LCD, the LCD must be busy flag judged, the display switch is set, the display start row is set, the page address is set, and the column address is set.

In the keyboard-LCD display system developed by ATmegal62:
(1) Since PC4-PC7 of ATmegal62 C port has JTAG interface function, it can no longer be used as I/O output port, unless the fuse bit JTAGEN is set to 1. (
2) When selecting the system clock source, the fuse bit must be configured correctly. The fuse bit determines the way the system uses the clock source and cannot be changed by ordinary programming when the MCU is running. Before debugging, the fuse bit should be correctly configured in the simulation system according to the selected clock source form and wake-up method to match the clock source with the fuse bit.
(3) During the debugging process, the negative voltage VDD-Vo of the LCD driver is required to be 13 V, otherwise it will not display normally.
4.2 Two-phase brushless DC motor controlled by ATmegal62
The two-phase brushless DC motor is an improved motor that combines the advantages of DC motor and AC motor. It adopts the position sensorless two-phase brushless DC motor control technology, which can make full use of the advantages of DC brushless motor, such as wide speed regulation range, no position sensor and not easy to damage, to achieve stepless speed change of the motor, low noise, high operating efficiency, control accuracy and reliability. Figure 2 shows an application example of using ATmegal62 to control a two-phase brushless DC motor. In the figure, ADC1 measures the given speed of the motor. In most devices, the speed of the motor is adjusted according to the external given value. The given value is an analog signal, so the ADC channel is required to measure the external speed. The PWM output needs to be constantly changed to reduce the difference between the motor speed and the external given value. Since the internal ADC and PWM are used, the Hall sensor is not required to measure the motor speed. The ADC (analog/digital converter) channel of ATmegal62 measures the induced electromotive force to control the commutation of the motor. The induced electromotive force flowing through the passive stator coil determines the direction of the motor. By changing the value of the PWM register to control the PWM duty cycle, a PWM signal with a pulse width that changes with the modulation wave is formed. The PWM signal is used to control the on and off of the power switch to supply power to the motor armature winding. The magnitude of the phase current and the energy transmitted to the motor armature winding are determined by the on and off time of the power switch. At the same time, the phase current and the energy transmitted to the motor determine the torque and speed of the motor, thereby achieving closed-loop control of the speed.

When ATmegal62 controls a sensorless two-phase brushless DC motor:
(1) When PWM controls the motor speed, the PWM base frequency must be greater than 20 kHz, and the power dissipation of the driving transistor must be determined by the PWM switching frequency;
(2) When controlling the voltage of the active coil, the PWM base frequency must be close to 20 kHz;
(3) When using ADC to measure the induced voltage, the ADC clock selection should ensure that ATmegal62 has enough time to handle interrupts.
4.3 Data collection and transmission of asynchronous serial communication ports
ATmegal62 has two full-duplex universal synchronous/asynchronous serial ports, which is a significant feature that distinguishes it from AVR series devices. Users can communicate data between devices more flexibly at low cost. The USARTn transceiver module of ATmegal62 is divided into three parts: clock generator, data transmitter and receiver. There are three completely independent interrupts: TX transmission completed, TX transmission register empty and RX reception completed. The highest baud rate can reach 115 200 b/s, and there is a dedicated high-precision baud rate generator that does not occupy the timer/counter. Figure 3 is an application example of using the asynchronous serial communication port of ATmegal62 to realize data collection and transmission. The motor driver SMD-401 controls the speed and direction of the stepper motor through the control signal output by the ATmegal62 PC port. The stepper motor drives the intelligent sensor to rotate. The trigger signal output by the sending end of the ATmegal62 serial port O triggers the sensor to collect data. The collected data is sent to the receiving end of the ATmegal62 serial port O through MAX232. After the necessary processing in ATmegal62, the data is transferred to the host computer through the serial port l through NAX488.

When implementing asynchronous serial communication port data collection and transmission on ATmegal62, the following issues should be noted:
(1) The source code generated by ICCAVR may not match the selected device, so the initialization program should be checked according to the actual situation.
(2) The baud rate register UBRROH of ATmegal62 and the control and status register UCSROC of USARTO share the same unit address. If the URSSEL0 bit is not set, the received baud rate will be wrong.
(3) Ensure that the sending and receiving baud rates are the same or within the allowable error range, and the sending and receiving must have the same data format.

5 Conclusion
This article introduces the characteristics of ATmegal62 and its application examples in practical projects. ATmegal62 has most of the functions of other devices in the AVR series, and has unique technology, full configuration, strong functions, high reliability, high speed, good anti-interference, low power consumption, high cost performance, simple hardware structure, flexible software design, wide application, low price, has certain practical value, and will play an increasingly important role in actual development.