Research on the Design of 8-bit Microcontroller Architecture

1. Introduction

Since the emergence of microcontrollers in the 1970s, they have developed rapidly and been widely used in the past 30 years. With the rapid development of microelectronics technology, microcontrollers have been widely used in household appliances, computing and peripherals, communications, industrial control, automated production, intelligent equipment, and instrumentation due to their outstanding advantages such as good performance, small size, low price, and complete functions. They have become the most effective tools for scientific research, teaching, and industrial technology transformation. From the simple microcontrollers that initially adopted the Princeton structure to the RISC microcontrollers that now commonly use the Harvard bus structure, microcontrollers have achieved rapid development ^[1] .

8-bit microcontrollers are currently the most widely used microcontrollers, and are also the market that most companies are committed to cultivating. The market and price competition are extremely fierce, and the speed of introducing new products with various multi-functional requirements and different specifications is also extremely fast. With the rapid development of integrated circuit and semiconductor process technology, the continuous competition and integration of FPGA and SOC technology, the design of electronic products is gradually developing in the direction of better system performance, lower power consumption, lower cost, higher reliability, and easier development. Therefore, the rapid launch of 8-bit microcontroller chips or IP Cores that meet market demand with high cost performance, low power consumption, and high economic benefits has become a hot spot for many companies to compete.

2. Current updates and design trends of 8-bit microcontrollers

For different microcontroller (MCU) product applications, it is necessary not only to consider the cost-effectiveness of MCUs from different manufacturers, but also to consider the application characteristics of MCUs under different instruction systems. In response to the emergence of new intelligent electronic products, people have been developing new MCU products suitable for different embedded system applications ^[2] . The instruction sets of MCU products from different manufacturers are different, especially the differences in the instruction set system architecture. For example, the widely used MCS51 series and PIC series microcontrollers in the market use CISC instruction system and RISC instruction system respectively.

Microcontrollers can be divided into several types according to their instruction systems, such as CISC, RISC, and RISC-like. The traditional MCS51 controller belongs to the CISC type, which has a high code density, but most instructions require multiple clock cycles to complete. The RISC type generally has a lower instruction density, but a very high instruction efficiency. The RISC-like type combines the advantages of CISC and RISC. The reason why RISC and RISC-like have such high instruction efficiency is due to the hard wiring structure and pipeline structure brought by the small instruction set. Simple instruction sets can use hard wiring to decode instructions without the need for microcode control, which improves the efficiency of decoding. The pipeline structure divides instructions into several steps to complete. When the pipeline is fully loaded, the average execution time (CPI) of each instruction is about 1 clock cycle ^[3] . Generally speaking, RISC is 50%-70% faster than the equivalent CISC, and is also easier to design and debug.

Therefore, the current product development and research and design of 8-bit microcontrollers are mainly based on compatibility with products that have been widely adopted by customers in the market, and constantly improving performance and reducing power consumption to adapt to market competition and technological development. For microcontroller products that originally used CISC instruction systems, RISC ideas have gradually been integrated into the endless series of updates; for microcontrollers using RISC instruction systems, more practices are still to continuously optimize and improve their entire system architecture in response to the needs of high performance and low power consumption, especially the improvement of pipeline structure is the most common. This article is proposed under this situation, mainly discussing the design technology of 8-bit microcontroller products with RISC architecture.

3. Structural characteristics and design principles of RISC microprocessors

Although there are different opinions in the industry about what features a RISC processor should have, various RISC structures have some common features ^[4] : ​​(1) Using the Harvard bus structure, most instructions are completed within one clock cycle to facilitate structural pipelining; (2) Using an independent and simple load/store structure; (3) Instruction decoding is usually hard-wired rather than micro-decoding to speed up execution; (4) Most instructions have a fixed format to simplify instruction encoding and decoding; (5) A small instruction set and a few addressing modes; (6) Data channel pipelines to make the processing process highly parallel; (7) Using a large-capacity high-speed register stack (or register file) to avoid exchanging data with the lower-speed system RAM as much as possible. Try to store the operation data in the register to reduce the number of memory accesses. Based on the above discussion, the following article focuses on the key technologies in the design of 8-bit RISC microcontrollers from the perspective of architecture, high performance and low power consumption.

4. Key technologies

4.1 Selection of RISC instruction set

The use of the controller system is closely related to the specification interface between software programming and hardware design, which is the instruction set of the microcontroller. The instruction system architecture (ISA) is the premise for the co-design of microprocessor hardware and software. The instruction set must be complete so that all computable functions can be implemented within a reasonable program space; and the instruction set must be efficient so that commonly used functions can be implemented with relatively few instructions. Therefore, the microcontroller system provided for application software development must have a complete and efficient instruction set.

The instruction set directly determines the internal hardware structure of the microcontroller, and is also the basis for compiling the user program to generate the target code. The final determination of the instruction set is closely related to the program memory, data memory, register variables and memory addressing mode required by the entire system, and they are mutually restricted. Each component and even a specific byte should have a unique address so that the instruction set can correctly identify and operate each component or byte. Therefore, there are a series of different measures for different products: 1) Weigh the length of the instruction from the required address length and the corresponding increase in registers; 2) Classify the instructions and determine the instruction byte format of each type to simplify the decoding logic of the operation control signal; 3) Add corresponding registers to make up for the lack of instruction byte length; 4) The allocation of instruction byte format should take into account the structural complexity of the corresponding components and the corresponding addressing mode; 5) Whether the memory, register, and I/O port are uniformly addressed. The above list is not exhaustive and there is no order of precedence, and it should be analyzed at the same time. The corresponding measures have different performance, power consumption, and design complexity, and should be considered uniformly.

The power consumption analysis of ISA should be considered from two aspects: instruction code capacity and instruction execution efficiency. The selection of technologies such as instruction set size, register variables, memory addressing mode, and pipeline structure are closely related to instruction code density. Research has found that appropriately adding some specific complex instructions to the RISC reduced instruction set is a feasible way to improve code density and ensure processor high performance and low power consumption. Therefore, instruction sets that can produce high instruction code density are undoubtedly the first choice for RISC low-power design ^[5] .

4.2 Paging Design of Register File with Shared Area

The main feature of RISC design concept is that all operations are register-oriented. Using register-register operation instructions to transfer data speeds up the process, simplifies the instruction control logic, and reduces the chip area of ​​the control components composed of hard-wired logic.

The number of bits of the fixed register address in the instruction will inevitably limit the number of registers, but the introduction of the segmentation and paging design concept of high-end processors can expand the addressing range. The fundamental starting point of the segmentation and paging design concept is to decompose the linear address of the memory into two-dimensional or multi-dimensional addresses; only the lowest-dimensional address is expressed in the instruction, and other facilities (such as segment number registers and page number registers) are used to store high-dimensional addresses. Generally, the register stack is divided into several pages, each of which has a fixed size, and only the page address of the register is used in the instruction. A page number register is set in the system-specific register, and the access to registers of different pages is switched by changing its content ^[6] .

In order to overcome the various defects of the simple paging mechanism, a paging design with a shared area is usually adopted, which not only reduces the number of bits of the register logical address in the instruction, but also allows access to the system register at any time, and facilitates the exchange of information between registers on different pages through the general registers in the shared area. Of course, there must also be corresponding methods and measures for mapping logical addresses to physical addresses.

4.3 Paging Design of Program Space

For the same reason as the register stack, if the complete program space address is used in the instruction, the size of the program space will be limited, so the program space is usually designed with paging, and a common program area is set up in different pages (if the instruction length fully meets the requirements of the program space address, this idea is not necessary). The design idea is similar to the register paging design with a shared area, so I will not go into details here. The only difference from the register common area is that the program common area provides a platform for the program to jump between different pages.

4.4 Pipeline Technology

Pipeline design is closely related to the 8-bit RISC microcontroller architecture and is the design core of the entire system. Its selection directly affects the performance and power consumption of the system.

Pipeline technology can maximize the use of microcontroller resources, allowing each component to work in every clock cycle, greatly improving efficiency. However, due to the strong dependence between the various segments of the pipeline, if not handled properly, the execution of the instruction will not achieve the expected results. Therefore, it is necessary to be familiar with the pipeline correlation and transfer issues. The first is resource conflict, that is, competing for the same functional component at the same time, generally accessing the memory at the same time, which requires pausing one beat of the pipeline; the second is data correlation conflict, which has three types: RAW, WAR, and WAW. To resolve this conflict, use the internal direct structure or delay the pipeline by one beat; the third is control transfer conflict, that is, for conditional jump instructions, the new PC value can only be determined based on the calculation result to determine whether to jump. The calculation result is obtained after the execution stage, which makes the pipeline lose a lot of performance. Generally, hardware is added to obtain the calculation result in advance to resolve this conflict ^[3] .

The longer the pipeline, the more serious the two major problems of correlation and transfer: on the one hand, the complexity of the hardware control circuit is greatly increased, and on the other hand, the pause of the pipeline beat leads to an increase in the CPI value and a decrease in system performance. Therefore, the longer the pipeline is, the better it is. Finding a balance between speed and efficiency is the most important thing.

There are many schemes in the pipeline design of 8-bit RISC microcontrollers. Different schemes correspond to different areas, speeds and power consumption. The specific selection should be considered from multiple aspects. First, a variety of specific pipeline structure schemes and their required strict timing should be derived from the system's operating rate requirements and the number and depth of pipelines; then, the advantages and disadvantages of each scheme should be judged from the aspects of system power consumption, area, performance and design complexity caused by pipeline-related and transfer problems; finally, the optimal scheme should be selected through compromise.

4.5 Low Power Technology

With the rapid development of the semiconductor industry, integrated circuits have entered the deep submicron stage. The clock frequency and chip integration of microprocessors have continued to increase. Power consumption has become a primary concern in many design fields, especially in high-performance microprocessors and portable electronic devices ^[7] .

When co-designing hardware and software and determining the instruction architecture based on the system function description, the design power consumption results caused by different design starting points will be very different. Therefore, the determination of the entire system architecture is undoubtedly the primary issue that should be considered in the low power consumption problem, which mainly reflects the following aspects ^[5] : 1) Optimize the instruction set according to the functional requirements as much as possible and simplify the decoding unit and execution unit of the system; 2) Realize a low power consumption structure by developing the parallelism of hardware and the pipeline execution of functional units; 3) Reasonably set and determine the capacity of memory and registers to reduce the number of required buses; 4) The division of each sub-module of the system hardware and the setting of different working states in the software are very important for optimizing power consumption.

5. Conclusion

Today, as the application of microcontrollers becomes increasingly widespread, higher requirements are placed on microcontrollers, hoping for faster speed, lower power consumption, low price, easy to learn and use, and fewer peripheral devices when composing the system. Therefore, the product development and design research of the 8-bit microcontroller, which is currently the most widely used, is particularly important. The architecture design is the key to the entire design, and all subsequent work depends on the designed architecture. This paper analyzes and discusses the issues that should be considered in the key technologies used in the 8-bit RISC architecture, which has certain research value and significance.

References:

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