EPP parallel port communication technology based on uPSD3254A single chip microcomputer

Introduction:

Since IBM introduced the PC, the parallel port has been a part of the PC. Initially, the parallel port was used to replace the serial port to drive high-performance dot matrix printers [1]. There are three transmission modes for parallel port communication: SPP, EPP, and ECP. The SPP mode is half-duplex and unidirectional, with a transmission rate of only 15KB/S; the EPP enhanced mode uses bidirectional half-duplex data transmission, with a transmission rate of up to 2MB/S; the ECP extended mode uses bidirectional full-duplex data transmission, with a transmission rate higher than EPP. In terms of design and implementation, the EPP mode is more flexible, simple, and reliable than the ECP mode, and has been used more in the industry [2]. This article introduces a design of an EPP enhanced parallel port based on uPSD3254A. Its core is to use the CPLD inside the uPSD323X to realize high-speed hardware communication between the EPP interface and the parallel port on the PC. In actual tests, the speed reached 900KB/S.

1 Introduction to the EPP protocol

The EPP protocol was jointly proposed by Intel, Xircom, and Zenith, and was published in the IEEE1284 standard in 1994. The EPP protocol has two standards, EPP1.7 and EPP1.9, which can be set in the PC's BIOS/Peripheral Setup/Parallel Port Mode [3]. Unlike traditional parallel port standards that use software to implement handshakes, the EPP interface protocol uses hardware automatic handshakes to achieve a communication rate of 500KB/s to 2MB/s.

1.1 Register and pin definition of EPP working mode

The PC parallel port uses a 25-pin DB-type cathode interface. The definition of the 25 pins in the EPP working mode is shown in Table 1.

Table 1 EPP protocol pin definition

Pin Number	EPP signal	direction	Is it reverse	illustrate
1	nWrite	Output	yes	A low level indicates writing, a high level indicates reading
2~9	Data0~7	Output / Input	no	data
10	Interrupt	enter	no	Rising edge triggered interrupt
11	Wait	enter	yes	Low level transmits data / address, high level ends transmission
12	Spare	enter	no	EPP is undefined and can be customized by the user
13	Spare	enter	no	EPP is undefined and can be customized by the user
14	nDstrb	Output	yes	Low level indicates data transmission
15	Spare	enter	no	EPP is undefined and can be customized by the user
16	nReset	Output	no	Low level is effective
17	nAstrb	Output	yes	Low level indicates address transmission
18~25	GND	—	—	land

In terms of registers, EPP defines 8 registers, inheriting 3 registers of SPP. EPP and SPP share status registers and control registers, ensuring the hardware and software compatibility of EPP mode and SPP mode. The register definitions are shown in Table 2. When setting the parallel port to EPP mode, you need to set the parallel port to work in EPP mode in the PC BIOS. The base address (BASE) of the register group is usually set to 0x378.

Table 2 EPP register definition

address	Port Name	Read / Write
BASE+0	SPP Data Port	Write
BASE+1	SPP/EPP Status Port	read
BASE+2	SPP/EPP control port	Write
BASE+3	EPP Address Port	Read / Write
BASE+4	EPP Data Port	Read / Write
BASE+5~+7	User-defined	—

1.2 EPP read and write cycles

In order to carry out effective EPP data communication, the EPP handshake timing must be followed. Compared with the software handshake of SPP, EPP uses hardware-completed handshake to achieve high-speed data communication. The EPP protocol is divided into four cycles: data write cycle, data read cycle, address write cycle and address read cycle. The data cycle is used to transmit data between the computer and the peripheral; the address cycle is used to transmit auxiliary information such as address, channel, command, control and status.

1.2.1 EPP data/address read cycle As shown in Figure 1,

the CPU read operation steps of the EPP data/address read cycle are as follows:

1) The program performs a read operation on the EPP data register (Base+4)/address register (Base+3) 2

) nDstrb/nAstrb is set low if the nWaite signal is low, otherwise wait

3) The host waits for nWaite to be high to indicate that the data is sent successfully

4) Read 8 bits of data/address from the parallel port

5) nDstrb/nAstrb is set high

6) EPP data/address read cycle is completed



Figure 1 EPP data/address read cycle

1.2.2 EPP data/address write cycle As shown in Figure 2,

the CPU write operation steps of the EPP data/address write cycle are as follows:

1) The program performs a write operation on the EPP data register (Base+4)/address register (Base+3)

2) Set the nWrite signal low (low indicates a write operation)

3) Send the data/address data to be written to the data bus

4) nDstrb/nAstrb is set low if the nWaite signal is low, otherwise wait

5) The host waits for the nWait handshake signal to be high to indicate successful transmission

6) nDstrb/nAstrb is set high

7) EPP data/address write cycle is completed


Figure 2 EPP data/address write cycle

When the EPP1.7 (Pre IEEE 1284) handshake standard is used, the nDstrb/nAstrb signal is directly set low to start a new read/write cycle regardless of whether nWait is low; if the EPP1.9 handshake standard is used, the nDstrb/nAstrb signal will be set low to start a new read/write cycle only when the nWait signal is low. However, both EPP1.7 and EPP1.9 require that a read/write cycle ends when the nWait signal is high [3].

Since nWait, nWrite, nDstrb, nAstrb and other signals are reversed after transmission (see Table 1), the timing in Figures 1 and 2 is considered from the PC side. The nWait signal represents the original signal sent by the microcontroller. The signal actually used on the PC side is the signal that is the inversion of the original signal sent by the microcontroller.

2 Introduction to uPSD323X and its development environment

ST's uPSD3254A is a Flash programmable system device with an 8032 core, with online programming capabilities and super confidentiality functions; 256+32Kbytes of Flash memory; 8K SDRAM on chip; 3000-gate programmable logic circuit (CPLD) with 16-bit macro units, which can realize some less complex interfaces and control functions such as EPP interface, 50 I/O pins, etc.

Since uPSD3254A uses an 8032 core, it can be fully supported by the Keil C51 programmer. PSDsoft EXPRESS is a software development environment based on the Windows platform developed by ST. All configuration and writing of peripherals such as address latches, Flash, and programmable logic circuits can be completed with just a click of the mouse. The operation of the programmable logic circuits of the uPSD3200 series devices using the PSDsoft EXPRESS tool is simple and intuitive. 3. EPP interface implementation based on uPSD3254A 3.1 Hardware interface The speed of the EPP enhanced parallel port can reach up to 500KB/s~2MB/s, which has high requirements for the interface of the peripherals. If the peripherals respond too slowly, the overall performance of the system will be greatly reduced. However, if programmable logic devices are used to make the interface response completely completed by hardware, the overall performance of the system will be greatly improved. This implementation scheme can reach the speed limit of the parallel port and has good confidentiality. The principle of the EPP interface (EPP1.9) peripheral hardware interface is shown in Figure 3. Figure 3 EPP interface peripheral hardware interface diagram In this design, uPSD3254A uses active continuous reception of data from the PC parallel port. When data is needed, it continuously receives data from the PC, otherwise the PC waits for the nWait signal to be valid. When the peripheral is ready to upload data to the PC, the PC uses an interrupt to receive the data from the peripheral. 3.2 CPLD logic programming In the PSDsoft EXPRESS tool, configure the PA port (D0~D7) as an input macro with a register type (PT clocked register) triggered by the rising edge of the clock, and configure PB4 (nWrite), PB6 (nDstrb), and PB7 (nAstrb) as CPLD logic input ports. The nDstrb signal and the nAstrb signal are each inverted and then ANDed together to form the clock of the input macro unit. The above configuration of PA and PB ports is expressed by the following equations: EPP_D0.LD = !nDstrb & !nAstrb; EEP_D1.LD = !nDstrb & ! nAstrb; EEP_D2.LD = !nDstrb & ! nAstrb; EEP_D3.LD = !nDstrb & !nAstrb; EEP_D4.LD = !nDstrb & ! nAstrb; EEP_D5.LD = !nDstrb & !nAstrb; EEP_D6.LD = !nDstrb & !nAstrb; EEP_D7.LD = !nDstrb & !nAstrb; nAstrb.LE = 1; nDstrb.LE = 1;




































Forward data transmission process: Take the case of the computer transmitting data to the peripheral microcontroller (i.e., the EPP data write cycle) as an example. The computer first sets the nWrite signal to low, indicating that it is a write cycle, and puts the data on the data bus at the same time, and then detects the nWait signal. If nWait is low, the nDstrb signal is set low. At this time, the !nDstrb & !nAstrb signals will have a rising edge, which will latch the data of the PA port into the input macro; when the microcontroller detects that nDstrb is low, the nWait signal will be high, indicating that the peripheral is busy receiving and processing data, and reading the data on the data bus at the same time. When the computer detects that the nWait signal is high, the data handshake signal nDstrb will be high, and the EPP data write cycle ends. The latching of the above EPP data and the generation of the nDstrb handshake signal are both generated by hardware, so the data transmission speed is fast. The entire data transmission process can be completed in one I/O cycle.

Data reverse transmission process: When the MCU is ready to upload data to the computer, uPSD3254A puts the data into the PA port and sets the Intr signal line low to request an interrupt from the computer. The computer uses a hardware driver to handle the hardware interrupt of the parallel port. The computer first sets the nWrite signal high to indicate that the current cycle is a read cycle. When the computer reads the EPP data port, it will also detect the nWait signal. If nWait is low, then set nDstrb low and read the data on the data bus. When the MCU detects that nDstrb is low, it immediately sets the nWait signal high. After nWait is high, the PC automatically sets the nDstrb signal high to complete a data cycle read process (relative to the PC).

3.3 MCU data receiving program

sbit nwait = P1^0;

sbit ERROR = P1^1;

sbit nDstrb = PB & 0x40;

void parallel_rcv(unsigned long rcv_count) //Parallel port receiving, rcv_count is the number of received bytes

{

unsigned long i;

rcv_data = (unsigned char * )&rcv_buffer;

reread_sign = 1; //Non-error state

while(reread_sign ==1)

{

for(i=0;i
{

nwait = 1; //The PC end is low after reversing, indicating that the peripheral is ready to receive

while(nDstrb) //Wait for nDstrb to be low to complete data transmission and latch

nwait = 0; //Complete the write cycle,

rcv_data[i] = UPSD_xreg.IMC_A; //Read data from the latched input macro

} //Receive completed

ERROR = error_check(rcv_data); //Detect error, 1 for correct, 0 for errorif

(ERROR)

{

reread_sign = 0; //If there is no error, exit the while loop

}

else

{

ERROR = 1; //If there is an error in the check, continue the while loop

}

}

This program is a subroutine for microcontroller data reception (i.e. PC writes data), where rcv_buffer is the receiving buffer area, and error_check is for checking the received data. If an error occurs, the user-defined pin 12 is set low. When the PC reads the status register and finds that the user-defined status is low, it resends the data to ensure the reliability of communication.

References :

[1] Yu Zhangguo, Li Zhongli, Zhang Xiaoqin, Li Leimin. Design of parallel communication system between AVR and PC based on EPP protocol. PLC&FA, 2004: (5)
[2] Huo Xiaofang. Interface technology of EPP enhanced parallel port using 68HC908GP32 microcontroller. Microcontroller and Embedded System Application, 2006: (4)
[3] Interfacing the Enhanced Parallel Port.pdf. http://www.beyondlogic.org

Author profile:

Fang Yaoxiang (1982-), male, Master student of School of Electrical and Information Engineering, Hunan University, Hunan Province, research direction: electronic technology application.

Li Fuhai (1964-), male, from Guangxi, Associate Professor of School of Electrical and Information Engineering, Hunan University, current research field: digital signal processing.

Hu Zhaobin (1963-), male, from Shaanxi, Chief Engineer of Shenzhen Mei'an Co., Ltd., current research direction: industrial printing technology.