Data Merger Converter Designed Based on EPM7128

The data switch has a high transmission rate. When it communicates with the serial port, the data is divided into two parts before sending and sent to the serial port separately. Then the data of each serial port is merged together and converted into PCM stream through the data merger converter. This paper introduces the data merger converter designed based on CPLD chip EPM7128.

1 Data Merger Converter Hardware Circuit

EPM7128 is a programmable large-scale logic device, a product of ALTERA's MAX7000 series. It has the characteristics of high impedance and electrically erasable. It has 2500 available gate units, a maximum delay of 5ns between pins, and an operating voltage of +5V.

IDT7205 is a FIFO type asynchronous read/write memory chip with a capacity of 8192×9 bits, an access time of 12ns, three flags: empty, half full, and full, a maximum power consumption of 660mW, and an operating voltage of +5V.

MSM4860DX belongs to the 5X86 series of PC104 embedded system, with AMD-133MHz CPU, two serial ports COM1 and COM2, one LPT parallel port, one ELOPPY interface, one IDE interface, one VGA/LCD interface, one AT-KEYBOARD interface, 16 interrupts, rated power of 8W, working voltage of +5V.

1.2 Data Merger Converter Circuit Block Diagram 2.2 Data Shifting Part Let the frequency of PCMCLK be f(MHz), then the frequency of FRAMECLK is f/8, because the frame length is 64, so: frame frequency = f/(8×64), PCM stream rate = f(bit/s). The frequency divider ratio is set by software, so the rate of PCM stream is programmable.

The block diagram of the programmable data merge converter circuit is shown in Figure 1. In the figure, DB is the data bus, AB is the address bus, R and W are read and write signal lines respectively, INT5, INT7, INT10 INT11 are four interrupts, CS1, CS2 and CS3 are the chip select signals sent to the frequency divider and two serial ports by the address decoder Addr-encoder generated inside the CPLD, ORG is the oscillation pulse sent to the frequency divider by the crystal oscillator, CLK is the pulse FRAMECLK and PCMCLK output by the frequency divider, WFIFO and RFIFO are the read and write pulses of the access FIFO containing address information generated by the CPLD, DATA_IN1 and DATA_IN2 are the serial port input data, PCM_DATA is the PCM stream output by the data merge converter, PCMCLKA is the output code synchronization clock, and WORLDCLKA is the output word synchronization clock.

1.3 Circuit Operation Analysis

The crystal oscillator sends the clock pulse to the frequency divider, which contains two programmable timers. The frequency divider sends the controllable FRAMECLK and PCMCLK to the CPLD, which forms three pulse signals through logical combination inside the CPLD. One pulse signal controls the counter to form two frame rate interrupt trigger pulses, INT5 and INT7. The CPU writes to the FIFO immediately after receiving the interrupt; another pulse signal controls the shift register to convert parallel data into a serial data PCM stream; the third pulse signal forms RFIFO to continuously read the FIFO. After the two serial ports receive external data through interrupt mode (INT10, INT11), they are temporarily stored in the buffer and written to the FIFO according to a certain format by the interrupt INT5 control.

2 CPLD internal logic circuit

The internal logic circuit of CPLD is shown in Figure 2. In the figure, the dotted box is the internal circuit of CPLD, and the outside of the dotted box is the I/O port of CPLD.

2.1 Address Decoder

The address decoder Addr-encoder is generated in VHDL language. The output of Addr-encoder includes the enable pulse ENB of the bus driver chip 74245, the enable pulse DIR of the bus transmission direction, the write FIFO operation pulse WFIFO, the chip select CS1, CS2 and CS3 of the divider and serial port, the FIFO data empty and full flag pulse RFIFOFLAG, and the FIFO reset clock pulse WCTRL.

The FRAMECLK cycle is 8 bits of PCMCLK, and they are all pulses sent by frequency division. FRAMECLK is used as the read signal of FIFO after inversion, and as the word synchronization clock after two inversions. PCMCLK is directly used as the clock trigger pulse of shift register 74165, and the low level output after the two are ANDed is used as the trigger level of 74165 heavy data. Their signal timing is shown in Figure 3.

From the timing diagrams of the three, we can see that every time the last bit of a byte is shifted, the FIFO data is read under the trigger of the inverted falling edge of the FRAMECLK pulse. At this time, the load enable 74165STD of 74165 happens to be low (NAND result), completing the loading of all data, and then a new round of data shifting begins under the action of the rising edge of the PCMCLK pulse.

2.3 Frame length counter part

Two 74161s are designed to be a 1/64 frequency divider, also called a frame length counter. The clock of this counter is FRAMECLK. The output of the counter has the highest two bits logically ANDed as interrupt INT7, and the output of the AND gate and the second highest bits logically XORed as interrupt INT5. In this way, INT7 is half a cycle earlier than INT5 in terms of timing. After the reset starts, the INT7 pulse is generated first, triggering the interrupt. After the COU interrupt, 64 bytes of data are written to the FIFO in the service program, and then the interrupt INT7 is masked. After half a cycle, there are 32 bytes of data left in the FIFO (so the read pulse of the FIFO is inversely proportional to the FRAMECLK). Then the interrupt INT5 arrives, and after the CPU responds, another 64 bytes of data are written to the FIFO, so that the FIFO always has data (to avoid the read FIFO falling exactly between the two write FIFOs, and the FIFO is read dead due to no data). In this way, every time the interrupt INT5 arrives, 64 bytes are written to the FIFO, and it repeats over and over again, so 64 bytes are set as the frame length.

3 Software Design

outp(0x303,0x36);//Mode 3, square wave. //

outp(0x300,0x50);//timer0, the division ratio is 80. //

outp(0x300,0x00);

outp(0x303,0x74);//Mode 2, pulse. //

outp(0x301,0x08);//timer1, the division ratio is 8. //

outp(0x301,0x00);

Data Merge:

if((com1_count%24)= =0); //The 24 bytes of data from serial port 1 are placed at positions 4 to 27 of the array Frame. //

{

com_buf1[com1_count++]=db1; //Serial port 1 receives data//

int Original_Counter;

Original_Counter=com1_count/24;

memcpy(Frame[Original_Counter-1]+4,&com_buf1[com1_count-24],24);

}

if((com2_count%24)= =0); //The 24 bytes of data from serial port 2 are placed at positions 28 to 51 of the array Frame. //

{

com_buf2[com2_count++]=db2; //Serial port 2 receives data //

int Original_Counter;

Original_Counter=com2_count/24;

Memcpy(Frame[Original_Counter-1]+28,&com_buf2[com2_count-24],24); //The merged data is placed in the Frame array. //

Write FIFO:

void Send_To_Fifo(int number); //The Send_To_Fifo function is part of the interrupt service routine. //

{

for(int i=0;i<64;i++)

outp(WFIFO,Frame[number][i]); //Send the array to FIFO to realize data merging//