Design of ADS1100 16-bit A/D converter using I2C bus

ADS1100 is a continuous self-calibrating analog/digital (A/D) converter powered by a single 2.7V~5.5V power supply. It has the advantages of high resolution, simple interface, proportional amplification, low power consumption and small size. ADS1100 uses the power supply voltage as the reference voltage, can perform proportional A/D conversion, and has differential input and up to 16-bit resolution.

ADS1100 can sample 8, 16, 32 or 128 times per second for A/D conversion, and provides an I2C port for external communication. The on-chip programmable gain amplifier (PGA) can provide up to 8 times gain, allowing small signals to be measured. ADS1100 has two working modes: single-cycle conversion mode and continuous cycle conversion mode. In the single-cycle conversion mode, the ADS1100 will automatically power down after performing an A/D conversion to reduce current consumption.

The main features of ADS1100 are as follows:

·16-bit no missing code;

·Continuous self-calibration;

·With programmable gain amplifier (gain = 1, 2, 4 or 8);

·Programmable data rate is 8s/s to 128s/s;

·With I2C port;

·Power supply voltage range is 2.7V to 5.5V;

·Low current consumption (90μA).


1 Pin Function and Internal Structure

1.1 Pin Function

The pin arrangement of ADS1100 is shown in Figure 1. It adopts a small SOT23-6 package. The functions of each pin are described as follows.

Pin 1 (VIN+): differential signal positive input terminal;

Pin 2 (GND): ground line;

Pin 3 (SCL): serial clock input terminal;

Pin 4 (SDA): serial data input/output terminal;

Pin 5 (VDD): +5V voltage input terminal;

Pin 6 (VIN-): differential signal negative input terminal.



1.2 Internal Structure

The internal structure block diagram of ADS1100 is shown in Figure 2. As can be seen from the figure, ADS1100 consists of a Δ-∑ analog/digital converter core with adjustable gain, a clock generator and an I2C interface. The analog/digital converter core of ADS1100 consists of a differential switched capacitor Δ-∑ regulator and a digital filter. The regulator is used to measure the voltage difference between the positive analog input and the negative analog input and compare it with the reference voltage. The digital filter receives a high-speed bit stream from the regulator. And output a code. The code is a number proportional to the input voltage. Considering the influence of the gain and offset errors of the regulator, the ADS1100 integrates a self-calibration circuit for automatic compensation.

2 Internal registers of ADS1100

There are two registers in ADS1100: output register and match register, both of which can be accessed through the I2C port. The output register contains the result of the last A/D conversion; the configuration register allows the user to change the working mode of ADS1100 and query the status of the circuit.



2.1 Output register

The 16-bit output register contains the result of the last A/D conversion, which is in binary complement format. After reset or power-on, the output register is cleared and remains at 0 until the first A/D conversion is completed. The format of the output register is shown in Table 1.

Table 1 Output register



2.2 Configuration register The

8-bit configuration register is used to control the working mode, data rate and programmable gain amplifier (PGA) settings of ADS1100. The default setting of the configuration register is 8CH, and the specific mode is as follows:



The ST/BSY bit indicates whether it is written or read. In single-cycle conversion mode, writing "1" to the ST/BSY bit causes the start of conversion, and writing "0" has no effect. In continuous mode, the ADS1100 ignores the value of ST/BSY.

When read in single-cycle conversion mode, ST/BSY indicates whether the analog/digital converter is busy with a conversion. If ST/BSY is read as "1", it indicates that the analog/digital converter is currently busy and the conversion is in progress; if it is read as "0", it indicates that no conversion is currently in progress and the last conversion result is stored in the output register. In continuous mode, ST/BSY is always read as "1".



Bits 6 and 5 are reserved bits and must be set to "0".

The SC bit is used to control the working mode of the ADS1100. When SC is "1", the ADS1100 works in single-cycle conversion mode; when SC is "0", the ADS1100 works in continuous conversion mode. The default setting of this bit is 0.

Bit 3 and Bit 2 (DR bit) are used to control the data rate of the ADS1100, and the control method is listed in Table 2.

Table 2 DR bit



Bits 1 and 0 (PGA bit) are used to control the gain setting of the ADS1100, and the control method is listed in Table 3.

Table 3 PGA bit



3 ADS1100 read and write operations

3.1 ADS1100 read operation

The user can read the contents of the output register and configuration register from the ADS1100. However, to do this, the ADS1100 must be addressed and 3 bytes must be read from the device. The first 2 bytes are the contents of the output register, and the third byte is the content of the configuration register.

It is invalid to read more than 3 bytes from the AD1100. All bytes starting from the fourth byte will be FFH. The timing of the ADS1100 read operation is shown in Figure 3.



3.2 ADS1100 write operation

The user can write new content to the configuration register (but cannot change the content of the output register). To do this, address the ADS1100 for writing and write a byte to the ADS1100 configuration register. The timing of the write operation to the ADS1100 is shown in Figure 4.

4 Application Circuit

Figure 5 is a specific application circuit of the ADS1100 in a dynamometer. According to the design requirements, the output signal of the sensor needs to be converted and amplified. This system uses the low offset and low drift OP07 operational amplifier to amplify and convert the front-stage signal, and uses TL062 for secondary amplification and zero input adjustment. In order to improve the stability of the input signal, the signal should be transmitted to the differential signal input of the ADS1100 through the LM310 emitter follower.