MCS-51 MCU External Interrupt Software Programming

MCS-51 microcontroller has multiple interrupt sources. Taking 8051 as an example, there are 5 interrupt sources, two external interrupts, two timing interrupts and one serial interrupt. In this section, we will discuss the software programming of external interrupts.
External interrupts are interrupts caused by external reasons, and there are two interrupt sources. They are external interrupt 0 (INT0) and external interrupt 1 (INT1). The interrupt request signal is input by pins P3.2 (INT0) and P3.3 (INT1).

There are two modes of external interrupt request signals, one is level mode and the other is pulse mode. It can be defined by the definition of relevant control bits.

The level mode is low level effective. The external interrupt will be activated only when the valid low level is sampled at the interrupt request input end (INT0) and (INT1) of the microcontroller.

The pulse mode is effective at the negative jump edge of the pulse, that is, when the interrupt request input end is sampled in two adjacent machine cycles, if the previous one is high and the next one is low, it is a valid interrupt request. This requires that in this interrupt mode, the pulse width of the interrupt request signal must be greater than one machine cycle to ensure that the level change can be sampled by the microcontroller. The control bits of the external interrupt request mode of

the timer control register (TCON)

are in bit 88 (IT0) and bit 8A (IT1) of the timing control register TCON (address 88H). When IT0 (IT1) = 0, it is level mode, and IT0 (IT1) = 1, it is pulse mode. At the same time, bit 89 (IE0) and bit 8B (IE1) in this register are external interrupt request flag bits. When the CPU samples a valid interrupt request at the INT0 (INT1) terminal, this bit is set to 1 by hardware. After the interrupt response is completed and the interrupt service is turned to, it is automatically cleared to 0 by hardware.

Interrupt Enable Control Register (IE)

Below we explain the relevant control bits: ·EA——interrupt enable general control bit, EA=0, interrupts are always disabled, all interrupts are disabled. EA=1, interrupts are always enabled. After the general enable bit is turned on, the enable or disable of each interrupt is determined by the setting of each interrupt enable control bit. ·EX0(EX1)——external interrupt enable control bit, EX0(EX1)=0, disable external interrupts. EX0(EX1)=1, enable external interrupts. ·ET0(ET1)——timing/counting interrupt enable control bit, ET0(ET1)=0, disable timing/counting interrupts. ET0(ET1)=1, enable timing/counting interrupts. ·ES——serial interrupt enable control bit, ES=0, disable serial interrupts. ES=1, enable serial interrupts. The enable and disable of interrupts are the opening and closing of interrupts. Interrupt enable means opening interrupts, and interrupt disable means closing interrupts. From the above description, we can see that the interrupt enable of MCS-51 is controlled through two levels, with the EA bit as the general interrupt control bit and each interrupt control bit as the sub-control bit. When the general interrupt bit is in the disabled state, the entire interrupt is disabled regardless of whether the sub-control bit is enabled or disabled. Only when EA=1 (enabled) can each sub-control bit set its own interrupt enable and disable. After the MCS-51 microcontroller is reset, IE=00H, so the interrupt is in the disabled state. It is worth mentioning that the microcontroller will not automatically turn off the interrupt after responding to the interrupt, so after entering the interrupt service program, the interrupt should be disabled by software instructions. Interrupt Priority Control Register (IP) The interrupt priority control of MCS-51 is relatively simple, with only two limited levels of high and low. The priority level of each interrupt source is controlled by the priority register (IP).

·PX0——External interrupt 0 (INT0) priority control bit. ·PT0——Timer interrupt 0 (T0) priority control bit. ·PX1——External interrupt 1 (INT1) priority control bit. ·PT1——Timer interrupt 1 (T1) priority control bit. ·PS——Serial interrupt (ES) priority control bit. Control bit = 0, priority is low. Control bit = 1, priority is high. Interrupt priority is for interrupt nesting service, and the control principle is: (1) Low priority interrupt cannot interrupt high priority interrupt service, while high priority interrupt service can interrupt low priority interrupt service. (2) If the same level interrupt has been responded, other interrupts will be disabled. (3) If multiple interrupt sources of the same level appear at the same time, the CPU will determine which interrupt is responded in the query order, and the order is: external interrupt 0→timer interrupt 0→external interrupt 1→timer interrupt 1→serial interrupt. Status setting of interrupt control registers In applications, we can use the interrupt system through the corresponding control registers, so from the perspective of use, these control registers are user-oriented. These control registers can be byte-addressed or bit-addressed, that is, the addressing of the bit state can use either byte operation instructions or bit operation instructions, for example: MOV IE,#81H. If using bit operation instructions, it can also be written as: SETB EA SETB EX0. For general external interrupt programs, we can arrange them like this: ORG 0000H; Main program entry START: AJMP MAIN ORG 0003H; External interrupt program entry AJMP INT00 MAIN: MOV IE,#81H; Allow general interrupts and external interrupts ...; Main program ... ... INT00: ...; External interrupt service program ... RETI; Interrupt return