Simulation verification and emulation based on 8051 core SoC

[page] 1 Overview

With the development of integrated circuit process technology and the rapid improvement of EDA design level, the ability and technology of system on chip (SOC) design based on intellectual property (IP) core has been greatly improved. With this technology, the entire system including microprocessor, ASIC, memory and peripherals can be integrated into one chip. In the process of SoC chip design, due to the widespread use and mature technology of 8051 series microcontrollers, many SoC chip designers often use 8051 when selecting 8-bit processors as cores. The design of SoC chip is very complicated. It not only needs to consider the system composition of chip IP core, software and hardware co-design, and integration of different processes, but also needs to consider how to realize the simulation verification of the chip in the design process and the realization of the simulation device for the chip after the design is successful, so as to promote the rapid promotion of the designed system chip.

2 SoC chip design technology

2.1 Software and Hardware Co-design Process

SoC chip is a chip design technology based on reusable IP cores and using hardware-software co-design as the main design method [1]. The SoC design process proposed in reference [2] is shown in Figure 1.

After the system chip is divided into software and hardware, the design is basically divided into two parts: chip hardware design and software co-design. Chip hardware design includes hardware description, timing design, verification, etc.; software co-design should consider instruction sets, instruction compilation systems, development integration environments, simulation equipment, etc. In order to achieve the goal of listing as soon as possible, these two aspects are required to be carried out in parallel, and even before the chip is listed, the corresponding development equipment and simulation environment should be established. For chips that need program masking, this requirement is even more urgent.

2.2 SoC Design for Fixed Network Short Message Phone

The chip is a system chip designed according to China Telecom's requirements for fixed-line short message phones. It can be widely used in caller ID (CID) phones and fixed-line short message phones.

The system chip integrates the CPU and multiple analog function modules (CID part) into one chip, using 8051 as the CPU core, and the instruction set is fully compatible with the standard 8051; the CID part is composed of IP cores such as FSK modem, DTMF (dual tone multi-frequency) dialing, CAS (CPE Alerting Signal) signal detection, and ringing detection. This is a digital-analog hybrid system chip with complete telephone functions. The system structure is shown in Figure 2.

In the design, the 8051 core and each functional IP core exchange data through registers and data buses.

The 8051 has 256 bytes of RAM, of which the last 128 bytes are special function registers. In the chip design, we define the registers used by the CID circuit (a total of 12) within this range.

The working process of the chip is as follows: after detecting the ringing signal, the ringing detection module sets the corresponding bit in the RING_F register, generates an interrupt or performs CPU round-robin detection; after responding to the signal, the software sets the FSK enable register in FSK_F, and the FSK demodulator works. After receiving the data, FSK sets the data ready register in FSK_F, generates an interrupt or CPU round-robin detection, and the software reads the data through the data bus; the CAS module detects according to the CAS capture time register in CAS_F, and after receiving the CAS signal, sets the corresponding register in CAS_F to generate an interrupt; the DTMF signal generation module sends a DTMF signal according to the content of the DTMF_F register.

3 System-on-Chip Verification and Simulator Design Solution

3.1 System-on-Chip Verification Issues

After the hardware and software design of the system chip is completed, the system verification is carried out according to the process requirements, which requires the construction of a verification platform. For digital circuits, the use of FPGA can basically realize the complete verification of chip design; while for mixed digital and analog circuit system chips, verification is very complicated. In this design, since each peripheral analog IP core has a corresponding module on the market, it is possible to consider organically combining FPGA and these analog chips to realize the verification of the system chip.

3.2 Design Goals of the Simulator

An 8051 emulator system includes emulator, compiler, integrated development and debugging simulation environment, etc. When designing SoC chips based on 8051 core, in order to speed up R&D, shorten time to market, and reduce development costs, consider using mature integrated development environments and development devices on the market that are used by many users, such as KEIL.

3.3 Chip Verification and Simulator Design Solution

As can be seen in the previous description, in the design of this chip, since the standard 8051 core is used, its instruction system and architecture are basically unchanged, but some special registers are mapped to peripheral modules, and the interrupt sources are also expanded. Therefore, the key to the design of verification and simulator lies in whether the status of these registers can be correctly reflected or the work of these peripheral modules can be controlled through registers.

In the system chip design process, the design of the simulator is synchronized with the chip design or even ahead of it, so there is no ready-made CPU chip as the simulator core; and simply combining the CPU with functional chips such as FSK, DTMF, CAS, etc. to replace the CPU chip cannot achieve complete simulation and simulation, especially the status of peripheral simulation modules cannot be obtained.

Here, we use FPGA and FSK, DTMF, CAS and other functional chips to form an analog CPU to replace the designed system chip. The system structure can be seen in Figure 3. In Figure 3, the 8051 core and digital interface are implemented by FPGA; in the CID part, FSK, DTMF, CAS, ring detection and other modules are implemented by corresponding hardware modules.

Modules such as FSK, DTMF, CAS, and ring detection correspond to the corresponding registers of 8051 in FPGA through interfaces, so that when these peripheral modules are in action, they can be correctly mapped in the 8051 registers; conversely, changes in the corresponding registers in FPGA will also cause the action of these peripheral modules.

Figure 3 is a short message system chip simulation solution based on a general 8051 simulator. The simulation CPU module integrates FPGA and CID chips and circuits. The module is connected to the simulation board using pins consistent with the 8051 definition. For the simulation board, the commands and operations of the module are

◇Fully compatible

Existing integrated development and simulation environment;

◇Simplifies the verification of mixed-analog and digital designs;

◇After improvement, general simulators can be used to simulate and debug hardware and software;

◇Since FPGA can be reprogrammed as the chip is improved, it increases the flexibility of design and verification;

◇Shortened development time and accelerated chip time to market.

4 Conclusion

The system chip verification and simulation scheme constructed by this scheme has been applied in our design. In fact, the idea of ​​this scheme can not only realize the verification and simulation of the system chip based on the 8051 core, but also can be used as a reference for the verification and simulation of other system chips.