Realization of FSK modulation based on C8051F060 single chip microcomputer controlling AD9833

introduction

In digital information transmission, baseband digital signals are usually modulated by a modulator to shift the frequency to a frequency band suitable for information transmission. 2FSK uses digital signals to modulate the frequency of the carrier (frequency shift keying). Due to its advantages of simple method, easy implementation, strong noise and fading resistance, it has been widely used in low and medium speed data transmission in modern digital communication systems.

Direct digital frequency synthesis technology (DDS) introduces advanced digital processing technology and methods into the field of signal synthesis. DDS devices use high-speed digital circuits and high-speed D/A conversion technology, and have the advantages of short frequency conversion time, high frequency resolution, high frequency stability, and fast programmable switching of output signal frequency and phase, which can realize full digital modulation of signals.

Introduction of DDS chip - AD9833

The AD9833 is a fully integrated DDS chip that only requires an external reference clock, a low-precision resistor, and some decoupling capacitors to generate a sine wave up to 12.5MHz. In addition to generating RF signals, the circuit is also widely used in various modulation and demodulation schemes, all of which are used in the digital domain.

The internal circuit of AD9833 includes two parts: digital devices and analog devices. It is mainly composed of phase accumulator (composed of adder and phase register), ROM waveform lookup table, digital-to-analog converter DAC and low-pass filter LPF. The basic structural principle of AD9833 is shown in Figure 1. Among them, M is the frequency control word, FMCLK is the clock frequency, the phase accumulator accumulates with a step size of M under the control of the clock FMCLK, and the output of the phase register is added to the phase control word and input into the address of the sine lookup table. The sine lookup table contains the digital amplitude information of a sine wave cycle, and each address corresponds to a phase point in the range of 0°~360° in the sine wave. The lookup table maps the input address phase information into a digital signal S(n) of the sine wave amplitude, which is converted into a step wave S(t) by the D/A converter, and then smoothed by a low-pass filter to obtain a synthesized signal waveform. Its shape depends on the amplitude code stored in the waveform ROM, so DDS can generate any waveform. The output sine wave frequency is: fOUT=M(fMCK/228), where M is the frequency control word, which is given by external programming and has a range of 0≤M≤228-1.

Hardware circuit connection

This design uses Silicon Labs' fully integrated mixed-signal system-on-chip C8051F060 to control AD9833. C8051F060 has a large number of digital resources that need to be used through 4 low-end I/O ports P0, P1, P2 and P3. Each pin of P0, P1, P2 and P3 can be defined as a general-purpose port I/O pin or assigned to a digital peripheral or function (for example: UART0 or INT1). Regardless of whether the pin is assigned to a digital peripheral or as a general-purpose I/O, the status of the port I/O pin can always be obtained by reading the corresponding data register.

When AD9833 is connected to the microcontroller C8051F060, the three I/O ports of the microcontroller are used to connect to AD9833. FSYNC (control input, low level is effective) is connected to the programmable pin P0.7 of the microcontroller, SCLK (serial clock input) is connected to the programmable pin P0.4, and SDATA (serial data input) is connected to the programmable pin P0.5. The three programmable pins can be programmed by software to realize data transmission. The hardware circuit connection is shown in Figure 2. The microcontroller generates control signals and waveform parameters, and transmits data to AD9833 through the serial interface. The sine wave signal output by AD9833 is then output after low-pass filtering.

Software Control

Write data to the control register

The timing of the microcontroller transmitting data to AD9833 is shown in Figure 3: The FSYNC pin is an enable pin, level-triggered, and low level is valid. When performing serial data transmission, the FSYNC pin must be set low. In this case, the data of the falling edge of 16 SCLKs are sent to the input shift register of the AD9833. FSYNC can be set high at the falling edge of the 16th SCLK. Of course, multiple 16-bit data can be loaded continuously, and FSYNC is set high only at the falling edge of the 16th SCLK of the last data. It should be noted that SCLK must be high before FSYNC starts to become low (when writing data).

When the microcontroller writes 16-bit data to AD9833, the high bit is in front and the low bit is in the back. Use software to simulate the clock signal and chip select signal. The procedure for transmitting data is as follows:

SCLK =1; //clock signal

FSYNC=1;

Delay(100) ; Delay subroutine

FSYNC=0; //Chip select is valid

for(i=0;i<16;i++)

{ SDATA="datas"&0x8000;

SCLK=0; //Data is sent to the I/O port on the falling edge of the clock signal.

Delay(50) ;

SCLK=1;

datas=datas<<1; //16-bit data is sent from high to low

}

Delay(50) ;

FSYNC=1;

SCLK=0;

Data writing method

Setting D15D14 in the control register = 00 means that data is written to the control register; setting B28 (D13) = 1 means that 28-bit data can be written to the frequency register continuously. By default, the lower 14-bit frequency word is written first, and then the higher 14-bit frequency word is continuously written to the frequency register; setting B28 (D13) = 0 means that 28-bit data is written to the frequency register twice. At this time, it is used in conjunction with the value of HLB (when HLB = 1, the higher 14-bit frequency word is allowed to be written to the frequency register, and when HLB = 0, the lower 14-bit frequency word is allowed to be written to the frequency register). Therefore, the data written to the control register can be: 0010 0000 0000 0000, which means setting a continuous 28-bit frequency word. The data writing flow chart is shown in Figure 4.

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Select Frequency Register

Since there are two frequency registers in the AD9833 chip, namely FREQ0 and FREQ1, it is necessary to determine which one the frequency control word is written into. This can be selected by setting the value of D15D14. When D15D14=01, it means that the 14-bit frequency word will be written into FREQ0; when D15D14=10, it means that the 14-bit frequency word will be written into FREQ1. Taking the output frequency of 7230Hz as an example, the frequency word written into frequency register 1 is introduced.

The lower 14 bits of data written are: 1011 0110 0001 1110, which means that the lower 14 bits of frequency word are written into FREQ1.

The high 14 bits of data written are: 1000 0000 0000 1011, which means that the high 14 bits of the frequency word are written into FREQ1.

Main program design

First, initialize the C8051F060 microcontroller, including initializing the microcontroller crystal oscillator, initializing the port, defining the I/O interface and cross switch that control the AD9833, and then initializing the AD9833. When the AD9833 is initialized, in order to avoid false output from the DAC, RESET must be set to 1 (RESET will not reset the frequency, phase and control registers). RESET will not be set to 0 until the configuration is completed and output is required; the waveform can be observed at the output of the DAC in 8-9 MCLK clock cycles after RESET is 0. The AD9833 initialization flow chart is shown in Figure 5. Then, write the control word (0x2000) of the frequency register 0. When performing FSK modulation, the two frequency registers of the AD9833 are loaded with different frequency values. In this experiment, the frequency register 0 is loaded with a low frequency of 6830Hz, and the frequency register 1 is loaded with a high frequency of 7230Hz. The frequency register is selected by setting the FSELECT bit of the control register of the AD9833. The main program flow is shown in Figure 6.

Experimental Results

The FSK modulation signal can be observed on the oscilloscope. For the convenience of screenshot, a sine signal with a frequency of 7230Hz is set to be observed on the oscilloscope. Figure 7 is the spectrum of the sine signal with a frequency of 7230Hz after low-pass filtering. It can be seen from Figure 7 that the actual output frequency is 7.22985Hz. Figure 8 is the corresponding time domain graph.

in conclusion

The FSK modulation signal designed in this experiment has strong practical value in engineering and has been successfully applied in underground acoustic wave transmission systems.