Satellite-borne intelligent 1394 terminal based on MC8051 soft core

1 Introduction

IEEE1394 is a high-speed serial bus that was originally developed by Apple as the FireWire bus in the mid-1980s. In 1995, IEEE formulated and promulgated the IEEE 1394-1995 standard, and in 2000 launched the IEEE 1394a standard, which supports transmission rates of 100Mbps, 200Mbps, and 400Mbps. In the latest IEEE1394B standard, the supported transmission rates have been increased to 800Mbps, 1.6Gbps, and 3.2Gbps. The IEEE1394 bus has been widely used in video transmission, network interconnection, and computer peripherals due to its high transmission rate [1]. At present, the requirements for high-speed real-time transmission of large amounts of data in aviation [2] and aerospace applications are constantly increasing. IEEE1394 has the characteristics of high data transmission rate and support for isochronous transmission, making it one of the choices for future satellite data buses.

In satellite applications, due to the diversity of tasks, the requirements for satellite bus interfaces are diverse. For example, some payloads do not have an integrated 1394 interface but need to use the 1394 bus to transmit data; or several payloads need to share a 1394 bus interface; or the payload itself does not have a control unit such as a microcontroller. In addition, the external data interfaces of various payloads are also different. At this time, a small, simple and easy-to-expand intelligent terminal with interface capabilities is needed to work with the payload. Since the IEEE1394 bus protocol is relatively complex, most practical applications use dedicated 1394 bus chips, and 1394 chips for dedicated systems support microprocessor interfaces. The common 1394 bus design uses a microprocessor plus a 1394 bus chip and a peripheral logic chip. This design requires a large number of chips, a large interface device, and it is more complicated to implement the expansion interface function.

Aiming at the actual needs of IEEE1394 satellite applications, this paper proposes a simple, low-power, miniaturized and easily expandable IEEE1394 intelligent terminal design based on the MC8051 soft core, which overcomes the shortcomings of the previous 1394 bus interface hardware circuit, multiple chips, and large size, and can easily expand other functions of the interface.

2 System Implementation Solution

The block diagram of the entire 1934 interface system is shown in Figure 1. The chip used is Actel's ProASIC Plus series FPGA chip APA600 based on FLASH technology. It has the characteristics of single-chip power-on, high performance and low power consumption [2]. Since it is power-on, the size of the circuit board is reduced, which helps to simplify the circuit design. The link layer chip TSB12LV32 [3] and physical layer chip TSB41AB [4] of TI are used in the scheme test. TSB12LV32 is a high-performance universal IEEE1394a link layer chip used for data transmission between the main controller and the 1394 physical layer chip and the external device connected to the link layer DM port. It is compatible with IEEE1394-1995 and P1394a standards and supports transmission rates of 400, 200 and 100Mbps. It provides an optional 8-bit/16-bit microcontroller interface with multiple operating modes, supporting up to 60MHz. The chip has built-in 2K-byte general interface FIFO and asynchronous transmission FIFO for data packet transmission between the microcontroller interface and the physical layer interface. The 8-bit/16-bit data movement port supports the sending and receiving of isochronous, asynchronous and data stream packets at 25MHZ. TSB41AB3 is a three-port physical layer chip compatible with IEEE 1394-1995 and P1394a standards at 400Mbps.

The FPGA integrates the open source 8051-compatible microcontroller IP core MC8051, which integrates the program memory, program memory, external data memory, UART and timer into one FPGA. Other required interfaces and logic units can be easily customized in the FPGA according to task requirements, such as AD/DA control, CAN bus, etc.

The above three parts can form a complete 1394 bus interface system for specific applications.

3 1394 bus interface design based on MC8051 IP

3.1 Oregano Systems MC8051 IP Core¬[5]

The MC8051 IP Core released by Oregano Systems is an open source IP Core based on GUN LGPL. It is fully compatible with the standard 8051 controller and has improved its architecture. When using the same clock frequency, the execution time of instructions is reduced to 1 to 4 clock cycles, so the speed is increased by more than ten times and the power consumption is reduced. The MC8051 model is a synthesizable RTL style, a completely synchronous design, with a single clock network, and its functions can be easily expanded by adjusting and modifying the VHDL code. It has 128 bytes of on-chip RAM, can support up to 64K of ROM and RAM, and integrates UART, timer, interrupt and 4 groups of 8-bit I/O ports.

3.2 MC8051 Design Key Points[page]

3.2.1 MC8051 parameter configuration

MC8051 provides parameterized design. By modifying the parameter values ​​in VHDL, the internal model can be easily modified, such as the number of UARTs, the number of timers, the selection of multipliers, etc. In this application system, multiplication and division operations are not required, so the constants C_IMPL_MUL, C_IMPL_DIV and C_IMPL_DA are set to 0 in the configuration file mc8051_p.vhd.

3.2.2 Clock and RAM Design

The highest clock frequency synthesized by MC8051 IP core on Actel's APA600 is about 15MHZ. In order to minimize the baud rate error of the serial port used for debugging, SmartGen in Actel Libero is used to generate a clock of 11.0592MHz as the system clock.

The internal RAM and RAM required by MC8051 should be implemented by calling the bottom unit of the device. Take the 128-byte internal RAM as an example. Use SmartGen to generate a 128*8 dual-port RAM ram128_8.vhd, and then instantiate it in mc8051_ram.vhd.
3.2.3 ROM Design

MC8051 is fully compatible with standard 8051 chips and can be developed using the KEIL uVision development environment. When creating a project file, select Oregano Systems' 8051 IP Core in Select Device, then compile the written 51 program to generate a HEX file. You need to get the program data from the HEX file. Here is a brief introduction to the HEX file format. The HEX file is composed of any number of hexadecimal records, each of which contains 5 fields, which are arranged in the following format [6]:

:llaaaatt[dd…]cc

HEX files all start with a colon. ll is the data length field, which indicates the number of data bytes in the record; aaaa is the address field, which identifies the starting address of the data bytes in the record; tt is the record type field. The hex files generated by the 51 program have only two record types, including data record (00) and file end record (01); dd is the data field, which indicates a byte of data.

The Actel APA series FPGA selected does not have the underlying ROM unit, so VHDL is used to design and implement the ROM. By understanding the format of the HEX file, a program is written to read data and address information from the HEX file, and then generate the mc8051_rom.vhd file, in which the program data is stored in the array file in the form of constants.

3.2.4 Interface between MC8051 and TSB32LV32

The link layer chip microprocessor interface includes a 16-bit wide data bus and a 7-bit wide address bus. By setting the status of the three ports of the link layer chip COLDFIRE, M8BIT_SIZ0, and MCMODE_SIZE, you can get various different operation modes of the microprocessor interface. In this design, it is set to 16-bit MCS-MCA handshake mode.

Instantiate MC8051_top in the system top-level file and connect MC8051 with the 1394 link layer chip TSB12LV32.

The 4 I/O ports of MC8051 are separated into input and output, so each group can be configured as input or output. We use MCS and MWR to control the connection between DM and P1 and P2 ports.

3.3 1394 bus control implementation based on MC8051

MC8051 reads and sets the internal registers of the link layer and physical layer through the microcontroller interface of TSB12LV32. The read and write of the registers of the link layer chip are directly operated through the microcontroller interface, while the read and write of the registers of the physical layer chip are realized by reading and writing the Phy Access Register of the link layer 24H.

Some internal registers of the 1394 chip need to be initialized when the system is powered on or set during operation, and some need to be monitored during operation to determine the system status. The asynchronous transmit FIFO and general receive FIFO inside the link layer are also accessed by reading and writing registers. Therefore, correctly reading and writing registers is a very important step in the implementation of the 1394 interface.

By correctly setting the control registers, DM port controller registers and other internal registers, the transmission and reception of various transmission modes of the 1394 bus can be realized.

Another major part of controlling the 1394 chip is the response and processing of interrupts. Connect the INT pin of the TSB12LV32 chip to the int0 of the MC8051, and detect the interruption through the falling edge of int0. There are two registers in the TSB12LV32 chip that are related to interrupts. Set the corresponding bit in the interrupt mask register of 10H to 1, and the response bit of the 0CH interrupt register will jump to a high level, and the corresponding interrupt will be generated at the same time. When an interrupt occurs, the INT pin becomes a low level, and to clear the interrupt, you need to write 1 to the corresponding bit of the interrupt register. Therefore, when an interrupt occurs, we can read the value of the interrupt register to see what kind of interrupt has occurred, and then make the correct response.

The flowchart of the main program is as follows:

4 Conclusion

According to the scheme introduced in this paper, we designed and developed a 1394 bus interface based on mc8051. After testing, the 1394 bus system works normally. The bus interface has the characteristics of high integration, small size, high transmission rate, etc. At the same time, it can easily expand the interface function according to the actual task needs. The scheme introduced in this paper has reference significance for the research and development of the 1394 bus interface.

The author's innovation is to apply the MC8051 soft core to the design of satellite-borne intelligent 1394 terminal.