Using FIFO to implement the interface between A/D and ARM processor

The 18-bit input/output port of CY7C4255 is controlled by a separate clock and enable signal. The input port is controlled by a continuous write clock (WCLK) and a write enable signal (WEN). When the write enable WEN is valid, the data is continuously written into the FIFO memory at the rising edge of the WCLK signal in each clock cycle. Similarly, the output port is controlled by a continuous read clock (RCLK) and a read enable signal (REN), and there is an output enable pin (OE). If it is a single clock operation, the read/write clocks can be connected together; in asynchronous read/write applications, the two clocks can be independent, and the clock frequency can be up to 100 MHz. Depth expansion can be achieved by using the cascade input (WXI, RXI), cascade output (WXO, RXO) and first load (FL) pins provided by the chip.

1.3 ARM processor LPC2210

LPC2210 is a microcontroller based on a 16/32-bit 144-pin ARM7TDMI-S core that supports real-time simulation and embedded tracing. It contains the ARM7 local bus that interfaces the ARM7TDMI-S core with the on-chip memory controller, the AMBA high-performance bus (AHB) that interfaces with the interrupt controller, and the VLSI peripheral bus (VPB, a compatible superset of the ARM AMBA bus) that connects the on-chip peripheral functions. LPC2210 has 16KB on-chip static RAM; the connection between on-chip peripherals and device pins is controlled by a pin connection module, which is controlled by software to meet the requirements of peripheral functions and pins in specific applications; the memory can be configured into 4 groups through the external memory interface, each with a capacity of up to 16MB and a data width of 8/16/32 bits; it has 2 32-bit timers (with 4 capture and 4 comparison channels), a PWM unit (6 outputs), a real-time clock and a watchdog; multiple serial interfaces include 2 16C550 industrial standard UARTs, a high-speed I2C interface (400kb/s) and 2 SPI interfaces; up to 76 general-purpose I/O ports (can withstand 5V voltage), 12 independent external interrupt pins EIN and CAP functions.

2 Interface Circuit

The interface circuit between AD7671 and LPC2210 is realized by using FIFO chip CY7C4255V, as shown in Figure 2. In the figure, the input range of AD7671 has been configured to ±5V, and its data port adopts a high-speed parallel interface; the data reading mode of the interface is set to the mode shown in Figure 1, where +5V and -5V are analog voltages. Since the voltage of the data interface between CY7C11255V and LPC2210 is 3.3V, the 3.3V digital voltage is input to the OVDD pin, so that the data interface voltage of AD7671 can be compatible with the data interface of the FIFO chip. ADR421 provides a +2.5V reference voltage for AD7671; the analog input end of AD7671 uses a driving circuit composed of a low noise factor excitation amplifier ADS021 to drive A137671.

The A/D conversion result output is directly connected to the FIFO data input terminal D0~D15. The conversion control is generated by a PWM output terminal of the ARM processor to generate a sampling control signal of the required sampling frequency, which is also used as the control of the input enable terminal of the FIFO. The BUSY output terminal of the AD767l is used as the input clock (WCLK) control signal of the FIFO. When the conversion is completed, BUSY (WCLK) changes from low to high. At this time, the FIFO write enable WEN is valid, and the conversion data is written into the FIFO memory at the rising edge of the WCLK (BUSY) signal. The LPC2210 ARM processor bus data width is configured as 16 bits, and the chip select signal nCS2, output enable signal nOE, and clock output XCLK of the EMC bus control the data reading of the FIFO. The half-full (HF) and full (FF) flags of the FIFO are connected to the two interrupt pins of the ARM, which can be selected and used in actual applications through programming; EF is connected to the PO.23 pin of the ARM as the empty query pin of the FIFO.

Conclusion

The use of FIFO devices as data buffer between high-speed A/D and ARM processor has the advantages of simple circuit structure and reliable performance; at the same time, it improves the working efficiency of the processor and makes control more convenient.