Design of VGA Interface for ARM Embedded Platform

Most embedded products use LCD as the display terminal, but in some applications that require large-screen display, industrial-grade LCDs are expensive, and existing large-screen displays (including CRT displays and LCD displays) generally use a unified 15-pin VGA display interface. Samsung's ARM9 chip S3C2410 is widely used in current embedded products due to its powerful functions and high cost performance. In the process of developing a blood rheology tester based on the ARM embedded platform, the author successfully used the high-performance video D/A conversion chip ADV7120 to convert the LCD scanning interface of the S3C2410 into a VGA interface, so that it can drive a display with a VGA interface.

1 VGA interface introduction

In recent years, the industry has developed many digital display interface protocols, the most typical of which is DVI (Digital Visual Interface). Since the digital interface standards have not yet been unified, manufacturers support their own standards, resulting in the delay in the standardization of digital interfaces. The VGA interface is an analog signal interface. As an interface standard in the display field for many years, it is still the most mature standard interface for all display terminals today. Now some high-end TVs also support the VGA interface.

The signal definitions of the 15-pin VGA interface are listed in Table 1. In addition to 2 NC signals, 3 display data buses and 5 GND signals, the more important signals are 3 RGB color component signals and 2 scan synchronization signals.

The color components in the VGA interface use the RS343 level standard. The peak-to-peak voltage of the RS343 level standard is 1 V. The four level ranges defined by this standard are:

White level --+0.714 V;

Black level -- +0.054 V;

Blanking level – 0 V;

Sync level --- 0.286 V.

2 Introduction to S3C2410 LCD Controller

Samsung's ARM9 chip S3C2410 is powerful and cost-effective, and has been widely used in current embedded products. S3C2410 has an LCD controller that can easily control the LCD display of the drive scanning interface.

2.1 Pin Function Information

The LCD controller provides scanning data transmission pins and timing control pins, which are described as follows:

VFRAME/VSYNC - frame synchronization signal between LCD controller and LCD driver. This signal tells the LCD screen that a new frame has started. The LCD controller inserts a VFRAME signal immediately after a frame is displayed to start displaying a new frame.

VLINE/HSYNC - Line synchronization pulse signal between LCD controller and LCD driver. This signal is used by LCD driver to transfer the content of horizontal line (row) shift register to LCD screen display. LCD controller inserts a VLINE signal after the whole line data is shifted into LCD driver.

VCLK--The pixel clock signal between the LCD controller and the LCD driver. The LCD controller sends data at the rising edge of VCLK, and the LCD driver samples at the falling edge of VCLK.

VM/VDEN - AC signal of LCD driver. VM signal is used by LCD driver to change voltage polarity of rows and columns, thus controlling the display of pixels. VM signal can be synchronized with each frame or with VLINE signal of variable data.

VD[23:0]--LCD pixel data output port.

2.2 Registers

The LCD control registers of S3C2410 are mainly LCDCON1 register, LCDCON2 register, LCDCON3 register, LCDCON4 register and LCDCON5 register. The settings of these registers are closely related to the display information, control timing and data transmission format. In the design, these registers need to be correctly set according to the specific information of the display device so that S3C2410 can normally control and drive different display screens.

2.3 Internal structure

The LCD controller of S3C2410 is used to transmit image data and generate corresponding control signals, which consists of REGBANK (control register group), LCDCD-MA (dedicated DMA), VIDPCS (video signal processing unit), LPC3600 and TIMEGEN (timing signal generation unit), as shown in Figure 1. REGBANK contains 17 programmable registers and several 256×16 palette memories, which are used to configure the LCD controller and set corresponding parameters; LCDCDMA provides a fast transmission channel for video signals, automatically takes out video data from the system frame buffer through the system bus and transmits it to the video signal processing unit; VIDPCS shapes the signal taken out from the dedicated DMA and improves the driving capability, and then outputs it to the external data port VD[23:0]; TIMEGEN and LPC3600 are responsible for generating the control timing required by the LCD.

3 VGA interface design

The high-performance video D/A conversion chip ADV7120 is used to convert the LCD scanning interface of S3C2410 into a VGA interface, and then the image is displayed on a monitor with a VGA interface.

3.1 ADV7120 Introduction

ADV7120 is a high-speed video digital-to-analog conversion chip produced by ADI in the United States. Its pixel scanning clock frequency has three levels: 30 MHz, 50 MHz, and 80 MHz. ADV7120 integrates three independent 8-bit high-speed D/A converters on a single chip, which can process red, green, and blue video data separately. It is particularly suitable for display terminals with high-resolution analog interfaces and application systems requiring high-speed D/A conversion.

The input and control signals of ADV7120 are very simple: 3 groups of 8-bit digital video data input terminals, corresponding to RGB video data respectively, and the data input terminals use standard TTL level interface; 4 video control signal lines include composite synchronization signal SYNC, blanking signal BLANK, white level reference signal REF WHITE and pixel clock signal CLOCK; an external 1.23 V digital-to-analog conversion reference voltage source and an output full-scale adjustment. There are only 4 output signal lines: analog RGB signals use high-resistance current source output mode, which can directly drive 75Ω coaxial transmission lines; the synchronous reference current output signal Isync is used to encode video synchronization information in the green video analog signal. [page]

3.2 Schematic Design

The synchronization signal of the VGA interface is consistent with the synchronization signal of the LCD scanning interface. Using ADV7120, the LCD scanning interface of S3C2410 can be easily converted into a VGA interface. The circuit principle is shown in Figure 2.

The synchronous scanning signals HSYNC and VSYNC in the S3C2410 processor interface are directly connected to the VGA interface, and the VDEN signal (display data valid signal) is used to control the ADV7120 chip. Since the ADV7120 has a very high precision requirement for the reference level, it cannot be replaced by a resistor divider circuit. Here, a 1.2 V voltage reference chip AD589 is used to generate the reference voltage. It should be noted in the circuit design that the analog ground and digital ground should be separated when laying out the PCB.

4 S3C2410 related register settings

Taking the 640×480 resolution, 60 Hz refresh rate, and 16-bit color display mode as an example, according to the VGA interface synchronization signal timing shown in Figure 3, the settings of the LCDCON1~LCDCON5 registers in the S3C2410 are introduced.

4.1 LCDCON1 Register

LINECNT: Status bit of line counter. Read only, no need to set.

CLKVAL: Parameter that determines the VCLK frequency. The formula is VCLK=HCLK／[(CLKVAL+1)×2], in Hz. The hardware system I use has HCLK=100 MHz, and the 640×480 display requires VCLK=20 MHz, so CLKVAL=1 needs to be set.

MMODE: Determines the speed at which VM changes. Select MMODE=O here, which is the change mode every frame.

PNRMODE: Determine the scanning mode. Select PNRMODE=0x3 for TFT LCD panel scanning mode.

BPPMODE: Determines the BPP (bits per pixel) mode. Here, select BPPMODE=0xC, which is TFT 16-bit mode.

ENVID: Data output and logic signal enable control bit. Select ENVID=1 to enable data output and logic control.

4.2 LCDCON2 Register

VBPD: Determines the delay time before the frame synchronization signal and frame data transmission. It is the ratio of the delay time before frame data transmission and the width of the line synchronization clock interval. As shown in Figure 3, VBPD=t3/t6=1.02mS/31.77μs=32.

LINEVAL: Determines the vertical size of the display. Formula: LINEVAL=YSIZE-1=479.

VFPD: Determines the delay time from the completion of frame data transmission to the arrival of the next frame synchronization signal. It is the ratio of the delay time after frame data transmission and the width of the line synchronization clock interval. As shown in Figure 3, VFPD=t5/t6=0.35 ms/31.77μs=11.

VSPW: Determines the frame synchronization clock pulse width, which is the ratio of the frame synchronization signal clock width to the line synchronization clock interval width. As shown in Figure 3, VSPW = t2/t6 = 0.06 ms/31.77μs = 2.

4.3 LCDCON3 Register

HBPD: Determines the delay time between the horizontal synchronization signal and the horizontal data transmission, and describes the number of VCLK pulses in the delay time before the horizontal data transmission. As shown in Figure 3, VBPD=t7×VCLK=1.89 μs×25MHz=47.

HOZAL: Determines the horizontal size of the display. The formula is HOZAL=XSIZE-1=639.

HFPD: Determines the delay time from the completion of row data transmission to the arrival of the next row synchronization signal, and describes the number of VCLK pulses within the delay time after row data transmission. As shown in Figure 3, HFPD=t9×VCLK=0.94 μs×25 MHz="24".

4.4 LCDCON4 Register

HSPW: Determines the horizontal synchronization clock pulse width. Describes the number of VCLK pulses within the horizontal synchronization pulse width time. As shown in Figure 3, HSPW = 3.77μs × 25 MHz = "94".

4.5 LCDCON5 Register

VSTATUS: vertical status. Read only, no need to set.

HSTATUS: Horizontal status. Read only, no need to set.

BPP24BL: Determines the display data storage format. Here, BPP24BL=0x0 is set to store in little-endian mode.

FRM565: Determine the 16-bit data output format. Here, set FRM565=0x1 for 5:6:5 format output.

INVVCLK: Determine the VCLK pulse valid edge polarity. Determine according to the screen information, here select INVVCLK=0xl, and data transmission starts when the VCLK rising edge arrives.

INVVLINE: Determines the polarity of the HSYNC pulse. As shown in Figure 3, it is negative polarity. Set INVVLINE = 0x1 to select a negative polarity pulse.

INVVFRAME: Determines the polarity of the VSYNC pulse. As can be seen from Figure 3, it is negative polarity, so set INVVFRAME = 0x1 to select a negative polarity pulse.

INVVD: Determine the pulse polarity of data output. Determine according to the screen information, here set INVVD = 0x0 to select positive polarity pulse.

INVVDEN: Determine the polarity of the VDEN signal. According to the screen information, set INVVDEN=0x0 here for a positive pulse.

[page]

INVPWREN: Determine the polarity of the PWREN signal. According to the screen information, set NVPWREN=0x0 here for a positive pulse.

INVLEND: Determine the polarity of the LEND signal. According to the screen information, set INVLEND=0x0 here for a positive pulse.

PWREN: PWREN signal output is enabled. Set PWREN = 0x1 to enable PWREN output.

ENLEND: LEND output signal is enabled. Set ENLEND = 0x1 to enable LEND output.

BSWP: Byte swap control bit. Set according to your needs. Here, set BSWP=0x0 to disable byte swap.

HWSWP: Half-word swap control bit. Set according to individual needs. Here, set HWSWP=0x1 to enable half-byte swap.

5 Discussion and Conclusion

The S3C2410 processor can drive the VGA interface in 24-bit color mode, but when the processor data bus is overloaded, the display effect is not ideal. The specific analysis of the required data bandwidth is as follows:

The data bandwidth of the S3C2410 processor operating in the 640×480×60 Hz×24-bit (resolution 640×480, refresh rate 60 Hz, 24-bit color) mode is: 640×480

0×60×4／(1 024×1 024)=70.3MB／s (24-bit color actually occupies 32-bit data volume), all of which need to be obtained from SDRAM through the system data bus using DMA. At a bus frequency of 100 MHz, the peak bandwidth of 32-bit memory of the S3C2410 processor is 100×32／8=400MB／s, and the actual bandwidth is only 100-200 MB／s. Then 70.3 MB／s of display data is too heavy for the S3C2410 processor, and the display screen often appears black for a short time. This is because the system bus is too busy, the data of the LCD scanning interface cannot keep up, and the frequency of the scanning clock temporarily slows down, causing the synchronization signal of the CRT display to not meet the specifications. If the 16-bit color mode is used, the data bandwidth is reduced to 640×480×60×2／(1 024×1 024)=35.2MB／s. In actual testing, working in 16-bit color mode, it can normally display 640×480 VGA graphics at 60 Hz.

Based on the above analysis, if you want to support high-resolution and high-refresh-rate displays, you need a relatively large data bandwidth, and you need to have high processor and bus frequencies. Current embedded processors have great limitations in these areas, but this design can fully support CRT displays in 640×480×60 Hz display mode with 16-bit color, and if LCD is used as the display interface, the LCD has different requirements for refresh rate than CRT displays, and the LCD can display normally at a refresh rate of 30 Hz. This design has great practical value and reference significance for solving large-screen display problems in ARM-based embedded systems.