Implementation of I2C device control method based on ARM

1 Introduction

The I2C bus is a two-wire serial bus developed by Philips. It is widely used to connect microcontrollers and peripheral devices because of its simplicity, high efficiency and low interconnection cost. AT91SAM7X256 is an industrial-grade chip based on ARM7 launched by Atmel in 2005. It is valued by developers in the embedded field for its small size, low power consumption, wide connection methods, rich processing resources and flexible control. This article introduces the use of the I2C controller TWI interface (two-wired interface) of AT91SAM7X256, and takes the I2C device E2PROM and calendar clock chip as examples to realize the reading and storage of time data by AT91SAM7X256. At the same time, in order to verify whether the reading and storage of time data are correct, the data in E2PROM is read to the memory for inspection using the online emulator J-LINK of AT91SAM7X256.

2 Hardware Design

2.1 Hardware module structure

The hardware module structure of the circuit is shown in Figure 1.

The TWI interface of AT91SAM7X256 consists of a clock line TWCK and a data line TWD, and the generated signal timing complies with the I2C bus specification; PCF8563 is an industrial-grade clock chip with I2C bus interface function launched by Philips; AT24C08 is a two-wire serial port E2PROM launched by Atmel that complies with the I2C specification. The TWCK and TWD of AT91SAM7X256 are connected to the SCL and SDA of the chip PCF8563 and AT24C08 respectively, and the CPU reads and stores the time data through the TWI interface. In order to ensure that the CPU does not conflict with the PCF8563 and AT24C08, this article connects the A2 pin of AT24C08 to a high level. Since the I2C bus is at a high level when idle, in order to realize the "wired AND" function, the devices connected to the bus are all open collectors, so the bus needs to be connected to an external pull-up resistor R. The TWI of AT91SAM7X256 has two working modes: master and slave. In this article, AT91SAM7X256 is the controller and should work in master mode.

2.2 TWI interface of AT91SAM7X256

The TWD and TWCK pins of AT91SAM7X256 are multiplexed with the I/O pins of the device. At the same time, AT91SAM7X256 adopts a power-saving solution that controls functional units individually. The power management unit PMC controls whether the clocks of each functional unit are working. Therefore, to use the TWI interface, you need to first configure TWD and TWCK to the peripheral connection and open circuit state, and then configure PMC to make the TWI clock in working state.

The TWI interface can provide a transmission rate of up to 400 kb/s. In order to adapt the data transmission rate to different applications, the signal frequency of TWCK can be adjusted by configuring the control register TWI_CWEG of the clock pulse generator.

The signal timing generated by the TWI interface complies with the I2C bus specification. When reading/writing 1 byte of data, the master device needs to provide the slave device address, internal address, read/write control, and start and stop flags. In the process of sending and receiving data, the control register TWI_CR, master mode register TWI_MMR, internal address register TWI_IADR, status register TWI_SR, transmission holding register TWI_THR and reception holding register TWI_RHR are mainly used. The slave device address is set in TWI_MMR, and the internal address of the slave device is set in TWI_IADR; whether to send the start signal and stop signal is set in TWI_CR; NAK (no response), OVER (operation error), TXRDY (send ready), RXRDY (receive ready), TX-COMP (transmission complete) and other status bits are obtained by querying WI_SR.

The process of writing data includes: when TWI_THR writes data, the CPU generates a start signal to start the transmission, the data in TWI_THR is transmitted by TWD after parallel-to-serial conversion, and when the CPU receives the response signal from the slave device, the TXRDY of TWI_SR will automatically set to "1", indicating that the data has been written to the slave device. The process of reading data includes: after the CPU sends a start signal, if the RXRDY bit of TWI_SR is "1", it means that there is data waiting to be received in TWI_RHR. When the data in TWI_RHR is read out, RXRDY is automatically set to "0". When the reading/writing of data is completed, the CPU will generate a stop signal to end the transmission, and the TXCOMP of TWI_SR will automatically set to "1".

2.3 How to use the PCF8563 calendar clock chip

According to the I2C protocol, PCF8563 has a unique device address of 0A2H. This article focuses on the method of reading the hour, minute, and second data of PCF8563. The internal registers used here include the control/status register 1 (address 00H), the second register (address 02H), the minute register (address 03H), and the hour register (address 04H). Since the hour, minute, and second data are stored in the register in BCD format, the high bits of each time register are invalid. [page]

In order to quickly read and write data, this article uses page write to write data to AT24C08; and uses a combination of "random read" and "sequential read" to read AT24C08 data.

3 Software Design

3.1 Design of TWI initialization program

According to the functional characteristics of TWI, the initialization of TWI includes the following 4 steps:

(1) Configure the PIO controller so that the multiplexed pin drives the TWI signal;

(2) Configure PMC to put the TWI clock in working state;

(3) Configure TWI to work in master mode. In this paper, the CPU is the master device, and the calendar and storage chip are slave devices;

(4) Set the data transmission rate and configure the TWI clock waveform generator register.

3.2 Design of PCF8563 Driver

In order to control the working mode of PCF8563, it is necessary to write control words to it; in order to obtain the time information output by PCF8563, it is necessary to perform a read operation on it. The process of reading/writing data is shown in Figure 3.

This article designs and writes the following read and write functions:

Among them, pTwi is a structure pointer, which points to a structure storing TWI registers. Each TWI register can be accessed through pTwi; address represents the device address; im_address represents the internal address of the device; data represents the variable pointer for reading and writing data.

Therefore, if PCF8563 is operated in normal mode and the "time" data is read, the following code can be used:

3.3 Design of AT24C08 Driver

Since AT24C08 consists of 4 pages with different device addresses and uses a continuous read and write data operation mode, the reading and writing of AT24C08 and PCF8563 have the following differences.

(1) First set the start flag of TWI_CR, then read/write the data of TWI interface through TWI_RHR and TWI_THR; before sending the last data, set the stop flag of TWI_CR.

(2) For reading and writing of multi-byte data, if all data have not been transmitted, the stop signal will not be sent. Therefore, it is necessary to determine whether to read TWI_RHR and write TWI_THR by judging TXRDY and RXRDY in the TWI_SR register, and whether the stop signal appears is used as the basis for judging whether to stop sending and receiving.

(3) Since the data volume and starting unit are random, it is possible that one page cannot be written. Therefore, it is necessary to calculate how many pages are required for a given data volume and starting unit parameters so that the device address can be changed when switching pages.

This article designs and writes the following read functions and write functions.

Among them, nb is the number of bytes read/written, and data is the first pointer to the array variable storing the read/write data.

3.4 Software Debugging and Operation

This article uses IAR development environment and J-LINK simulator to debug and load the software online. Call the function to complete the following program design: first, read a number of data from PCF8563 and write them into AT24C08; second, read the data in AT24C08 into the array variable. Set a breakpoint after reading the AT24C08 data in the program, observe the data stored in the array, and verify the correctness of the driver.

4 Conclusion

This paper introduces the use of PCF8563 and AT24C08. By analyzing the TWI interface control method of AT91SAM7X256 based on ARM core, the driver programs of PCF8563 and AT24C08 are designed to realize the reading and storage of clock data.

The driver module designed in this paper has been successfully used in the intelligent coal mine substation experimental system to complete the recording function of historical time data. At the same time, this paper provides a reference method for ARM to control multiple I2C devices.