Design of LCD display based on ARM and WindowsCE

1 Introduction

With the continuous development of electronic information technology, the application of embedded systems is becoming more and more extensive. In embedded electronic measurement systems, LCD (Liquid Crystal Display) is the main device for human-computer interaction. It has low power consumption, small size and excellent character and graphic display functions. Windows CE is an embedded real-time operating system. Its friendly graphical interface has become the mainstream operating system for embedded development. It uses the Graphics Device Interface (GDI) to process the graphics output of the program. The numerous functions provided by GDI can be used to easily output graphics and text on the LCD screen [1].

The principle of designing LCD system based on embedded processor Intel PXA270 and Windows CE provides a solution for embedded portable devices to maintain low power consumption under high brightness display conditions. It is suitable for high-end PDAs, portable media players, handheld navigators, portable medical and test equipment, etc. The following article will introduce the main design principles of the LCD device for railway locomotive fault diagnosis on-board device newly developed by the 608th Institute of China Aviation Industry.

2 LCD hardware system based on IntelPXA270

The system uses the Intel PXA270 processor based on the ARM processing core, 64MB of SDRAM, M-System's DOC (Disk On Chip) H3 chip as the storage system, and an external 16-bit 800×480 TFT display.

2.1 ARM processor IntelPXA270 and its LCD control

Intel PXA270 is an embedded processor based on ARM microprocessor core launched by Intel. Its main frequency can reach up to 624MHz. Intel PXA270 has added Wireless MMX technology, which greatly improves multimedia processing capabilities. It also adds Intel SpeedStep dynamic power management technology, which minimizes device power consumption while ensuring CPU performance.

The built-in LCD controller of Intel PXA270 provides an interface between the Intel PXA270 processor and the flat-panel display. The flat-panel displays it supports include passive DSTN LCD screens, active TFT LCD screens, and LCD screens with internal frame buffers. The railway locomotive fault diagnosis on-board device LCD device newly developed by the 608th Institute of China Aviation Industry uses a TFT LCD screen.

The LCD controller is used to transmit display data and generate necessary control signals. Table 1[2] shows the control signals of the LCD controller built into Intel PXA270:

Table 1 LCD controller control signals

The built-in LCD controller of Intel PXA270 supports multiple display modes, including pixel data format, display screen size, scanning mode, color mode, etc. The Intel PXA270 LCD controller has many registers for configuring different LCD screens and different display modes. The LCD controller has a dedicated DMA, which can automatically transfer display data from the frame memory to the LCD driver. Through the dedicated DMA, data can be displayed without CPU intervention.

2.2 TFT LCD Screen

The TFT LCD is a FG070053DSSWJGT1 display screen with a display screen size of 7 inches and a resolution of 800×480. It integrates an input control unit, a TFT display module, a scan driver IC, a backlight, a DC/DC voltage converter, a data driver IC, etc. Figure 1 shows the internal structure of the G070053DSSWJGT1 display screen [3].

Figure 1 TFT internal functions and interfaces

The timing required by the TFT LCD display consists of frame synchronization (VSYNC), line synchronization (HSYSNC), bit clock (DCLK) and data (Data[0:15]). Frame synchronization and line synchronization indicate the beginning of each frame and each line, as shown in Figure 2.

Figure 2 TFT LCD timing diagram

2.3 TFT screen display interface circuit [page]

Combined with the internal structure and timing diagram analysis of the LCD controller built into IntelPXA270 and the FG070053DSSWJGT1 LCD screen, the LCD display interface circuit is designed, mainly to connect the control signal of IntelPXA270 with the control pin of the LCD screen, as shown in Figure 3. The data sending pin of the LCD controller is connected to the data receiving pin of the FG070053DSSWJGT1 through the 16-bit data line, that is, (R0-R4, G0-G5, B0-B4) is connected to L_DD0-L_DD15; the frame clock, line clock, pixel clock, etc. are connected to the LCD screen; ADJ uses a PWM pulse with a voltage of 0-3.0V and a frequency of 20KHZ to adjust the brightness of the LCD screen backlight, which can effectively control power consumption while meeting user requirements. In Figure 3, the network label LCLK is the line clock control signal, FCLK is the frame clock control signal, PCLK is the pixel clock control signal, and OE is the data output enable signal. VDD is provided by a DC 5V regulated power supply. U/D is pulled down by a resistor to provide an up and down flip signal for the screen. L/R supports left and right flip control of the screen.

Figure 3 TFT LCD interface circuit

3 LCD display program design

LCD driver development under Windows CE is implemented using the Basic Graphics Engine (GPE) class [1] [5]. Before using the GPE class to write a driver, first analyze the requirements for the display device when using the GPE class to write a display driver. The memory layout requires the display device to use a linear frame buffer, and all display memory is continuous; then analyze the GPE class's requirements for the data format in the memory. The LCD screen is a top-down format, with pixel (0, 0) in the upper left corner and pixel (width-1, height-1) in the lower right corner. The stride of the frame buffer, which means the number of bytes in memory occupied by a scan line on the display device, should be an integer multiple of four bytes. Even if some useless bytes are filled at the end of each scan line, the CPU can access the entire frame buffer without making a "row" selection. The frame buffer should not use bit planes (bit planes are each color channel stored separately in the frame buffer).

The LCD controller built in Intel PXA270 is used, which integrates 7 channels of DMA and supports RGB modes with pixel depths of 2, 4, 8, 16, 18, and 24 bits, and is designed in 16-bit RGB mode. The image data is stored in the memory, and the frame data is accessed using DMA. The frame size and frame address are specified, which can meet the requirements of the linear frame buffer of the GPE class. The LCD control and LCD screen meet the hardware requirements of using the GPE class to implement the display driver under Windows CE.

3.1 Creating a GPE-based display driver

Using the GPE class simplifies the development of Windows CE display devices. The GPE class represents a display device and is a pure virtual class. This basic GPE class must be inherited when designing a display driver.

First, define a new class (class SA2Video) to inherit the GPE class. According to the requirements of the GPE class, implement the following functions:

NumModes ------Returns the display modes supported by the display driver.
GetModeInfo ------Returns information about the specified display mode, such as display pixel width and depth. It processes the display mode returned by the NumModes() function. When the SetModes() function is called, it always returns the first mode value in the mode configuration list.
SetModes ------Sets the display mode.
AllocSurface------Allocates a page. A page is just RAM or video RAM that stores pixel data. It is a block of memory. The GPESurf class can be used to represent a page on the system video memory. Ensure that a page is allocated on the video RAM.
SetPointerShape------Sets the cursor bitmap and cursor area.
MovePointer------Moves the cursor.
BltPrepare ------Called before a bit block transfer operation. If the driver supports operations before bit block transfer, it allows the driver to establish a hardware bit block transfer (blit) operation and returns an actual operation function to perform the bit block transfer (blit). The default Blit operation function is provided in the GPE class.
BltComplete------Executed after the block transfer is completed. If necessary, it allows the device to do any cleanup operations.
Line ------Called before and after line drawing. If called before drawing, this function can establish the hardware line drawing operation and then return to the GPE default line drawing operation. If called after drawing, this function can do any cleanup after line drawing operation.
InVBlank ------Flags whether the display is updated during the horizontal synchronization cycle.
These functions are empty functions in the source code of the GPE class, so the function overloading must be implemented in (class SA2Video).

3.2 Creating an LCD Controller Interface Driver

Creating an interface driver for the LCD controller is mainly about completing the hardware configuration, including the configuration of the LCD controller and the IO pin interface. First, configure the IO registers in the Intel PXA270 according to the circuit connection of the LCD display interface, and then configure the LCD controller according to the parameters provided by the external LCD screen, mainly configuring the TFT interface timing, such as frame clock, line clock, pixel clock, data output enable, etc. [6]. The XllpLCDInit() function in the xllp_lcd.c file implements the hardware initialization. The following is the key code of this function:

XLLP_STATUS_T XllpLCDInit(P_XLLP_LCD_T pXllpLCD)
{ XLLP_STATUS_T status = 0;
// Initialize IO interface and configure according to LCD connection circuit diagram
LCDSetupGPIOs(pXllpLCD);
// Initialize LCD controller and frame buffer
LCDInitController(pXllpLCD);
// Clear the status register of LCD controller
LCDClearStatusReg(pXllpLCD);
// Enable LCD controller and drive LCD screen to display data
LCDEnableController(pXllpLCD);
return status;
}

3.3 LCD controller display mode settings

WindowsCE GDI supports display devices with multiple color grayscale and color modes, from colors represented by only one bit to true 32-bit RGB modulated by a palette. Each format supports several different pixel arrangements, depending on whether access to the display memory supports single-byte, double-byte, or four-byte modes.

Use the following mask to extract the red, green, and blue values: The format in which each pixel is represented by 16 bits is a mask format and is not color-adjusted. We use two bytes to store each pixel. Combining the hardware circuit diagram of the TFT LCD display interface and the LCD controller built into the Intel PXA270, according to the instructions in the Intel PXA270 processor manual, the control pins need to be initialized [7]. In Figure 3, port 14 is used for frame clock control. Combining the Intel PXA270 data manual, we configure port 14 as the L_VSYNC function, which is implemented using the following statement:
GAFR0_L|=((GAFR0_L&～(1u<<29))|(1u<<28))
All display data lines L_DD0—L_DD15 are set as output ports and set as display data outputs. The program design is as follows:

[page]

p_GPIORegs-> GPDR1|=(XLLP_GPIO_BIT_L_DD0|XLLP_GPIO_BIT_L_DD1 |XLLP_GPIO_BIT_L_DD2
|XLLP_GPIO_BIT_L_DD3 | GPIO_BIT_L_DD6| XLLP_GPIO_BIT_L_DD7 |XLLP_GPIO_BIT_L_DD8|XLLP_GPIO_BIT_L_DD9 | |XLLP_GPIO_BIT_L_DD14|XLLP_GPIO_BIT_L_DD15); p_GPIORegs->GAFR1_U=(p_GPIORegs->GAFR1_U uses virtual addresses under WindowsCE. A mapping function converts the physical address used into a virtual address. This is required by the WindowsCE operating system. The mapping address The function is BOOL MapVirtualAddress().

Configure the LCD control register according to the display mode of the screen, including the mode of configuring the LCD control signal. By referring to the data sheet of Intel PXA270 and a series of calculations, the parameters are configured based on the TFT LCD timing diagram:

L_FCLK is the frame clock; L_LCLK_A0 is the line clock; L_BIAS is the clock enable; L_PCLK_WR is the pixel clock, LDD<17:0> is the pixel data, in this design we only use LDD<15:0>.
ENB: LCD data enable bit HSP: horizontal clock signal voltage polarity
0------LCD is not available 0------Horizontal clock is high level valid
1------LCD enable 1------Horizontal clock is low level valid
PCP: Pixel clock voltage polarity
0------Pixel data is sampled when the data pin is rising edge
1------Pixel data is sampled when the data pin is falling edge

(1) Definition of rows and columns:
PPL: The number of horizontal pixels on the LCD screen. The value is determined by the length of the LCD screen.
PPL = row width - 1.
In this design, the row width is 800, so PPL = 800-1;
LPP: The number of vertical pixels on the LCD screen. The value is determined by the width of the LCD screen.
LPP = column height - 1.
In this design, the column height is 480, so LPP = 480-1;
(2) L_PCLK_WR:
VCLK is the clock signal of the LCD controller. This signal is the pixel clock signal between the LCD controller and the LCD driver. When calculating VCLK, you need to first understand the frame rate range required by the LCD screen, and then set a value within the frame rate range as CLKVAL. The relationship between VCLK and CLKVAL can be calculated using the following formula: VCLK (Hz) = HCLK / ((CLKVAL + 1) x 2)
The minimum CLKVAL is 0, and the maximum CLKVAL is determined by the frame rate [8].
(3) Values ​​of various delays:
BFW: The delay length required at the beginning of a frame
EFW: The delay length required at the end of a frame
VSW: Definition of the width of the frame synchronization signal VSYNC
BLW: The delay length required at the beginning of a line
ELW: The delay length required at the end of a line
HSW: Definition of the width of the line synchronization signal HSYNC

4 Conclusion

LCD display design is based on embedded processor Intel PXA270 and Windows CE. LCD drives TFT display screen. Display mode is active single scan color mode. Pixel depth is 16-bit RGB format. Screen size is 800×480. By making full use of Intel PXA270 hardware resources, Intel PXA270 is used to control color display screen. Display brightness reaches 100 nits. Under high brightness of LCD, the power consumption of display is less than 365 mW, which overcomes the contradiction of high brightness accompanied by high power consumption of general TFT LCD. It supports the graphical display of Windows CE interface on user-customized TFT LCD screen. Since the designed hardware driver circuit only needs LCD controller to give frame synchronization signal, line synchronization signal, pixel clock, data enable signal and RGB data signal, the designed driver circuit can be flexibly transplanted to different platforms.