Design of CAN/PCI Intelligent Communication Card Based on ARM Controller LPC2294

LPC2294 is a powerful, ultra-low power 32-bit microcontroller with ARM7TDMI core launched by PHILIPS . It has rich on-chip resources and can fully meet the needs of general industrial control. At the same time, it can also reduce the complexity of system hardware design and improve system stability.

CAN (“Controller Area Network”) bus controller area network is a serial communication network that can effectively support distributed control or real-time control. CAN bus is gaining more and more attention and favor due to its high performance, high reliability and low cost. In order to effectively manage CAN nodes in industrial sites and give full play to the performance of CAN bus, the design and research of communication cards are very necessary. However, there are two shortcomings in similar products on the market.

First, there may be more than one CAN bus in a general industrial site, but the CAN interfaces on the currently designed communication cards are too few, which makes it difficult to centrally manage the equipment.

Second, currently the communication between two CAN network segments is mainly achieved through a one-to-one CAN bus bridge, but this method cannot solve the need to transmit data between several CAN network segments at the same time in industrial sites, and it is also easy to cause network confusion.

Therefore, the ARM controller LPC2294 selected in this design has four CAN controllers integrated inside, which fully complies with the CAN specification CAN2.0B standard and ISO11989-1 standard. The global acceptance filter can identify the 11-bit and 29-bit Rx identifiers of almost all buses. As the core component of this design, the use of LPC2294 can solve the above two problems well. It can not only take on the work of the main controller, but also serve as the data transmission controller of the CAN network to realize data exchange with nodes in the network.

1 Hardware Design

With the development of computers, except for a few specialized industrial computers that still use the ISA bus, the most commonly used bus on PCs is the PCI bus. The PCI bus is a high-performance 32/64-bit local bus for PCs launched by Intel. It can support multiple peripherals at the same time without being restricted by the processor. Its data throughput is very large (at a bus frequency of 33 MHz and 32-bit transmission, its peak value can be as high as 132 MB/s). The PCI bus will definitely replace the ISA bus due to its superior performance. Therefore, this paper designs an intelligent communication card with 4 CAN bus segments based on the PCI bus. Figure 1 is the overall hardware structure diagram of the communication card.

1.1 Implementation of PCI bus interface

The PCI bus has very strict specifications and good compatibility. However, the PCI bus protocol is also relatively complex. This design uses a dedicated PCI bus interface chip PCI9030 to implement the PCI bus interface of the gateway. PCI9030 is a low-cost PCI bus slave mode interface chip developed by PLX . The chip has low power consumption and complies with the PCI2.2 specification. When designing, users only need to consider the logic control circuit on the local bus side and the external EEP-ROM used for configuration, without having to consider the specific implementation method of the PCI protocol. This greatly simplifies the design difficulty and shortens the development cycle.

PCI9030 requires an EEPROM as initialization memory. When the system is loaded, PCI9030 first loads the initial data from the EEPROM and performs initial settings. Therefore, whether the information in the EEPROM is correct determines whether the PCI card is loaded and runs normally. This design uses ST93CS56 as the initialization memory of PCI9030, and its structural scheme is shown in Figure 2.

1.2 Implementation of CAN bus interface

There are two common methods to implement the CAN bus interface in this communication card:

(1) Implementation of independent CAN bus control chip

That is, Philips' SJA1000 independent CAN controller is used to implement the CAN protocol. The advantage of this method is that it can realize more complex functions and has good flexibility, but because it is an independent controller, designing a communication card with 4 CAN segments requires 4 SJA1000s , which will cause resource redundancy, the system will be larger, and the stability will be affected, and the design difficulty will be greater.

(2) Implementation of microcontroller with CAN interface

A representative example of this method is Philips' ARM chip LPC2294, which integrates 4 on-chip CAN bus controllers and can easily implement multi-channel CAN bus interfaces, reduce system size, and improve system stability.

Comparing the above two methods, in the traditional SJA1000 , the receiving filter can only meet some ID filtering with high regularity, or perform arbitrary filtering on a small number of IDs (generally less than 10-15), but it is difficult to implement more complex arbitrary ID filtering, which undoubtedly increases the burden of system software design and operation. The second design method is relatively simple. Since the LPC2294 microcontroller provides a global receiving identifier query function for all CAN controllers, it is easy to design more complex ID receiving filters, and the focus of its work is mainly on the software design of the ARM chip. This article adopts the second method to implement the CAN bus interface, and uses PCA82C250 as the CAN bus driver. At the same time, 6N137 is connected between the CAN controller and the CAN driver to reduce the electromagnetic interference of the CAN bus to the gateway card. Figure 3 shows the connection diagram of a CAN interface in LPC2294, and other interfaces are similar.

1.3 Hardware interface design between microcontroller and PCI9030

The hardware design between the microcontroller and PCI9030 is the core control part of the communication card. This design uses ALTERA's FPGA EPlC6 to implement the interface between the microcontroller and PCI9030. EPlC6 is an FPGA chip from ALTERA. It integrates 20 128×36 bits RAM modules. It can be easily programmed as the required "dual-port RAM", and then the uplink data (data sent by the CAN node to the PC) and the downlink data (data sent by the PC to the CAN node) are forwarded through the "dual-port RAM" cache. Since EPlC6 has a rich I/O port, the data format (32-bit/16-bit/8-bit) and transmission method can be flexibly selected. This article adopts the 16-bit multiplexing transmission mode.

EPlC6 also needs to be programmed to implement the logic control timing conversion between PCI9030 and ARM. Since the control signals of PCI9030 and ARM are not completely consistent, logic control timing conversion is required. At the same time, the local bus side of PCI9030 in this article adopts the address/data multiplexing mode, while the ARM controller adopts the non-multiplexing mode, so EPlC6 also needs to perform mode conversion: during the address cycle of PCI9030, LALE can be used to latch the 16-bit address into the internal register of EPlC6, and when the data cycle of PCI9030 comes, it will be sent to the address port and data port of ARM together with the data to facilitate ARM to use.

2 Software Design

2.1 Communication card software design

The software on the communication card mainly refers to the software program on the ARM controller. This article uses the ARM controller LPC2294 to implement intelligent data transmission path selection. LPC2294 is the control core of the communication card. It integrates 4 CAN controllers, each of which has a similar register structure to the independent CAN controller SJA1000 , except that the device register access is changed from the original 8-bit byte access to 32-bit double-word access. LPC2294 can realize data transmission control between the CAN segment and the host computer (including uplink data transmission and downlink data transmission) and data transmission control between different CAN segments (parallel data transmission).

LPC2294 provides a global receive identifier query function for all CAN controllers. It contains a 512×32 (2 k bytes) RAM, which can store 1 to 5 identifier tables in the RAM through software processing. The entire receive filter RAM can accommodate 1024 standard identifiers or 512 extended identifiers, or a mixture of two types of identifiers. Since the allowed table range is 2 k bytes, it can easily meet complex ID receive filtering requirements. LPC2294 can automatically receive and select the standard frame of the network segment in FullCAN mode, but this article does not use FullCAN mode. [page]

If a status and control register group (SOR) is set in the "dual-port RAM" of EPlC6, then the host computer can query the operating status of the communication card by accessing the register group. In order to effectively manage data transmission and prevent data loss during transmission, this design opens up a global data transceiver buffer area (GRTB) in the static RAM area inside the ARM, and its schematic diagram is shown in Figure 4.

In Figure 4, for a standard frame, it only has an 11-bit identifier, so the identifier bytes 3 and 4 in the figure are reserved. The frame format is used to distinguish whether the frame is a standard frame (0) or an extended frame (1). When RTR is 1, it means that the frame is a remote frame. The source segment number and destination segment number in the figure are used to indicate which network segment the frame comes from and to which network segment it will be sent (here the host computer is also treated as one of the segments). DLC indicates the number of data bytes transmitted.

2.2 Communication card operation process

After the system is powered on and reset, the system will first run the initialization program. The initialization of LPC2294 is mainly to initialize the global receive and transmit buffers and clear the values ​​in the status registers, etc. The initialization of PCI9030 is mainly to load the initial data from the EEPROM for initial settings. CAN initialization includes setting the mode, bus timing, interrupt enable, and identifier table. These settings can be achieved by assigning values ​​to the internal registers of the CAN chip. After successful initialization, the communication card will perform a self-test and enter the working state after confirming that the startup is normal. The program flow chart of this part is shown in Part A of Figure 5.

After the system enters the working state (part B in Figure 5), it will wait for an interrupt to occur. If there is one, it will enter the corresponding interrupt service routine. If it is data transmission, it will enter the data transmission subroutine, which mainly includes three parts:

(1) Downlink data transmission

Downlink data transmission refers to the host computer sending data to the CAN network segment. That is, the host computer writes the data into the "dual-port RAM" to wait for the LPC2294 to take the data away. The LPC2294 temporarily stores the data sent by the host computer in the global data transceiver buffer (GRTB), and then checks whether the matching destination segment has an idle transmission area (the TBS bit in CANSR is 1). If so, the data is written into the transmission area of ​​each network segment and sent. If all three transmission buffers of the matching network segment are busy, it will wait in a loop until more than one transmission buffer is empty before sending.

(2) Uplink data transmission

Uplink data transmission refers to the CAN segment sending data to the host computer. When the program detects that the receive interrupt bit (RI) in the CAN interrupt/capture register (CANICR) of a certain segment X is set, it will enter the receive interrupt service routine. At this time, the program will search for a matching identifier in the identifier table. The CAN controller will automatically search the table in the RAM of the receive filter and match it when receiving. As long as a matching value is found, a receive interrupt will be generated and the user will be notified to retain the information. Otherwise, the frame information will be automatically abandoned without generating a receive interrupt. If it only finds a matching value (in the source segment), it means that this data is only transmitted to the host computer. At this time, the program will save the received data information in the global data transceiver buffer (GRTB) in the format described above, waiting for LPC2294 to send it to the "dual-port RAM" of EPlC6 for the host computer to read.

(3) Parallel data transmission

When a receive interrupt occurs, the program will also search for matching identifiers in the identifier table. If more than one matching value is found, it means that other network segments need this data. At this time, the program will read the received data information into the global data transceiver buffer (GRTB) and then send the data to the matching network segment.

After calling the corresponding data transmission subroutine, the program will set the flag and return. If it is some other interrupt, it will go to the corresponding interrupt service program. If no interrupt occurs, check whether the PC needs to configure parameters, and finally perform a system self-check. This system will perform a self-check and upload a status report when the system is idle, so that users can understand the working status of the communication card at any time, which is of great significance to improving the working reliability of the system and the efficiency of error detection when a fault occurs.

2.3 Host computer program design

In this design, the upper computer software design program mainly includes the communication card bottom driver and user service program. Its design block diagram is shown in Figure 6.

The functions of the communication card bottom-level driver are mainly to configure the CAN bus interface, send and receive data on the CAN bus, monitor the CAN bus in real time, execute the send and receive commands of the user program, etc. CAN bus and PCI bus errors are both handled by interrupts and directly notified to the user program through the event kernel object.

The PCI user service program communicates with the system PCIDI (PCI device interface) through the PCI communication program, and the system completes the PCI protocol processing and data transmission. Users can conveniently set node parameters and query node status information on the designed host computer interface.

3 Conclusion

The CAN/PCI smart communication card designed in this paper uses the powerful ARM chip LPC2294 as the core control chip. Therefore, the communication card can simultaneously process the data transmission from 4 CAN buses to the host computer. For the communication needs between CAN network segments, this communication card can also meet them well and make the CAN network networking of industrial sites simpler.