Intel reveals more details about its mining chips-EEWORLD

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The media has noticed that Intel will give a presentation titled "Bonanza Mine: An Ultra-Low Voltage Energy Efficient Bitcoin Mining ASIC" at the upcoming ISSCC conference in late February. It has attracted a lot of attention because it confirms the fact that Intel is working hard to develop hardware that supports blockchain. Through various channels, we have been able to obtain more details about this chip ahead of the conference.

DS1 means there will be a demonstration

The more computing power a miner has, the more blockchain rewards that miner will receive over a period of time - it always becomes a competition between the big players to get a larger share of computing power to get more rewards. Initially, this went from CPUs to GPUs, FPGAs, and now hardware designed specifically to process blockchains and receive these rewards. The current state of Bitcoin mining is led by application-specific integrated circuits, or ASICs. There are companies in the industry, such as Bitmain and MicroBT, working with partners such as TSMC to create Bitcoin-specific chips as miners go after the proof-of-work-based cryptocurrency.

Hardware from AMD and NVIDIA was used when Bitcoin mining was GPU-focused, but as the Bitcoin algorithm could be accelerated further, ASICs were created. Currently, these GPUs are being used for ASIC-resistant algorithms and chains like Ethereum, which is part of the reason (but not the only reason) that gaming graphics cards are so expensive - if you can "earn" enough mining to pay off the card in a few weeks or months, it's a no-brainer for large mining operations. However, for Bitcoin, the trend for ASICs shows orders of magnitude better performance for the same power. Ultimately, these proof-of-work systems are limited by the amount of hardware available and the power available - Intel cites an estimated 91TWh annual electricity usage for Bitcoin today (although no mention is made of how that power is sourced).

Take the ASIC in WhatsMiner M30S-88T as an example

In the early days of ASICs, these were essentially FPGA-hardened IP blocks that scaled up and out. The need to quickly produce and enable silicon had it started in a very rushed manner, and the companies involved had limited experience with traditional silicon development and deployment timeframes. That was a few years ago, and some of these companies were using their 8th generation ASICs and were leading partners with major foundries on leading process technologies. Silicon was small, production volumes were high, and with the right advantages, it could be very profitable. For example, Bitmain’s next generation ASIC product had 384 chips installed in a system, and a single transaction had sold 78,000 systems (29.5 million chips) for $879 million to Marathon Digital Holdings, and that was just one customer. Sometimes in a gold rush, it’s the people selling the axes who make the money.

However, in the context of more traditional chip vendors, we haven’t seen much movement on this front. GPU vendors are battling miners and Ethereum, but there has been no real progress in terms of focused chips in this area – at least until Intel started hinting at it. Back in December, Intel’s Raja Koduri hinted that the company was moving into this area, and with a talk at ISSCC next month, this confirmed it. But we have more details.

Intel's first generation ASIC: BZM1

Intel has two generations of SHA-256 ASICs. The first was the BZM1, and was the subject of the ISSCC presentation. Intel is using a 7nm process to manufacture the chip. Exactly which one is not specified – the document we have says “7nm”, but the same document also refers to Intel 4 as “4nm”. This likely means that the BZM1 is being manufactured at Intel, which could be one of Intel’s first IDM 2.0 customers leveraging Intel’s internal custom design team – the SEC filing is co-signed by Intel’s general manager of custom accelerators for context.

The chip is 14.16 mm2 (hence a maximum of 4000 chips per wafer) and operates at 1.6 GHz, producing 137 gigahash per second (137GH) at 2.5 W. 25 of the chips are used in a deep board configuration, with a voltage stack of 335 mV per chip for a total of 8.875V main supply.

Notably, the minimum voltage of 335 mV per chip is very low. Intel says this is the most technologically advanced Bitcoin ASIC to date, using an ultra-low voltage design, specialized clocking strategies, and other circuit and microarchitecture optimizations — more details in the actual ISSCC presentation in February.

Intel will say at ISSCC that it takes 55 J per TH, although the math here doesn't make sense given the other numbers it provides. At 137 GH and 2.5 W, that means 18.2 W/TH. For context:

*Fees vary by Bitcoin. Prices listed as of January 20, 2022.

**Unverified single source

Intel's second generation ASIC: BZM2

Intel's second-generation chip has been listed in a filing with the SEC. According to the filing, it's called the BZM2, and it already has financial agreements in place with customers. The document is a four-year supply agreement between Intel and Griid Infrastructure, starting on September 8, 2021, for the BZM2 chip, which is designed for the SHA-256 cryptographic hash function. While the exact purchase agreement number has been redacted, Griid will provide an 18-month rolling forecast that Intel will work towards, with specific pre-order quantities and minimum deposits at the start of the agreement. The chips will be delivered by May 2023, although the contract can be extended. Intel offers no warranty on the chips other than DOA, and also provides three months of support after each batch of chips is delivered.

In the document, BZM2's details have been redacted.

There are two versions of the BZM2 that may differ in power and performance, but the specific numbers have been redacted. We have a source that says the BZM2 is built on TSMC N5 and offers 35 J/TH, which would be a 37% power saving over the first generation by the same standards. However, this information may not be correct; we are looking for a second source.

We're not sure why Intel is talking about its first-generation chips at ISSCC when it's already taking orders for second-generation hardware - it could simply be that Intel doesn't want to reveal details about its leading-edge hardware, despite new Intel CEO Pat Gelsinger's oft-repeated commitment to being more open.

Competition and Market

Bitmain’s latest generation is based on the TSMC N5 and exhibits nearly identical efficiency. We crunched numbers from the S19j Pro 104, which is built on the TSMC N7, and know that a full system with 384 chips draws 2750-3250 W of power. That works out to about 7-8 W per chip, which is 3x what Intel suggests its chips can do. We’ve also seen reports that these TSMC N7 chips have over a billion transistors each. In the race for density, we’ll see systems with 2-3x the number of chips. Regardless, this will be a way for Intel to fill up its 7nm fabs with small, high-yield silicon.

It is worth noting that if Intel ordered 29.5 million chips (at a price of $867 million, as mentioned above), at a perfect yield of 4,000 per wafer, nearly 7,500 wafers would be required. Intel cited market research saying it expects the cryptocurrency mining hardware market to grow by $2.8 billion between 2021-2025.

I spoke to a colleague who is more focused on the mining/ASIC space and he said that producing ASICs in the US could benefit the locale, language, and relationships and avoid the additional 25% tariff currently on mining hardware. My guess is that Intel will work with specific partners that have minimum order requirements for such hardware.

It’s unlikely to mean anything for the struggling GPU market – just hope they don’t put one on GPU boards as a way to help miners “recover” the cost of the GPUs themselves. We’re on a good timeline, right?

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