Research on the phenomenon of output lagging behind input in PLC

Abstract: Programmable Logic Controller (PLC) is a new type of general automatic control device, which has the advantages of powerful functions, flexible use, high reliability, good environmental adaptability, and simple programming. However, its disadvantages are: the working speed is slower than that of computers, and the output response to the input has a lag phenomenon; the use of medium and high-end PLCs requires users to have considerable computer knowledge. Therefore, when designing a PLC control system, it is very important to analyze and study the reasons for the lag in the input/output response of the PLC.
Keywords: PLC; input/output response; lag; ladder diagram 1

The results of the output lag input phenomenon in PLC

In the relay control circuit, each parallel circuit is simultaneously applied with voltage and works in parallel. Due to the mechanical inertia of the actual component action, contact competition may occur. In the ladder diagram, the action sequence of each programming element is executed in sequence according to the scanning order, or in a serial manner. When executing the ladder diagram program, it is serially scanned from top to bottom and from left to right, and contact competition will not occur. The
relay control circuit diagram and ladder diagram that look exactly the same on the surface may not produce exactly the same effects, and some effects may even be completely opposite. Figure 1-1 and Figure 1-2 show two sets of relay control circuit diagrams and ladder diagrams that are exactly the same in structure. The control purpose is to achieve the function of "when X0 acts, X1 acts, so that Y2 is self-holding and Y0 is reset".

In Figure (a), after X0 is activated, Y0 is energized and self-retained ,
and creates conditions for Y2 to be connected and self-retained. Then X1 is activated, energizing Y1, and the moving breakpoint of Y1 first cuts off Y0, resulting in the purpose of resetting Y0, but Y2 cannot be energized. In Figure (b), after X0 is activated, Y0 is "energized" and self-retained, and after X1 is activated, Y1 is "energized". Therefore, in the current scan cycle, when the program scans the following Y0 and Y1 moving contacts, because their coils are "energized" at this time, they are all in the connected state. In this way, Y2 can be "energized" and self-retained. When the next scan cycle comes, Y0 is reset, and the control purpose is achieved. 

In Figure (a), after X0 and X1 act successively, due to the inertia of Y3 and Y4, Y0 is reset after Y2 is powered on and self-maintained, achieving the control purpose. In Figure (b), when X1 does not act, Y1, Y3, and Y4 are all "powered". After X0 acts, Y0 "powers on" and self-maintains. When scanning to Y2, Y2 cannot be "powered". Even if X1 acts immediately after X0 acts, the sequential scan will reset Y0. As a result, Y2 still cannot be powered.
2 Analysis of the reasons for the lag of output response to input response

2.1 PLC program execution process
The execution process of PLC for user programs is carried out in the periodic sequential cycle scanning mode of the microprocessor. After the PLC is put into operation, it enters the program execution process, which is divided into three stages, namely input sampling, program execution, and output refresh. When the PLC starts running, it first clears the original contents of the input and output status registers, then performs self-diagnosis, self-checks the CPU and I/O components, and starts cyclic scanning after confirming that it is working normally. Each scanning process of PLC can be represented by Figure 1.

(1) The data in the input image register is written in the state of the input signal scanned in the input sampling phase. In this scanning cycle, it does not change with the change of the external input signal.
(2) The state of the output image register (which is contained in the component register) is determined by the execution result of the output instruction in the user program.
(3) The data in the output register is written in the output image register in the output refresh phase.
(4) The output state of the output terminal is determined by the data in the output latch.
(5) The input and output states required when executing the user program are read from the input image register and the output image register.
2.2 PLC input/output response hysteresis phenomenon
In the design of PLC control system, the most significant shortcoming is the input/output response hysteresis phenomenon. It takes a period of time from the input signal of the PLC input end to the output end of the PLC responding to the input change. This period of time is called response time or hysteresis time.
(1) The execution of the program is carried out according to the working cycle. Each working cycle is divided into three stages: input sampling, program execution, and output refresh. For example, the PLC ladder diagram shown in Figure 2 and the status table of each image register and output terminal during the program execution (Table 1) are analyzed as follows:
According to the three stages of program execution, the status of the X0 image register, Y2, Y0, Y1 image register and their output terminals can be filled in Table 1. The analysis is as follows:

In the first cycle, because X0 is OFF in the input sampling stage, X0 in the input image register is OFF, so the Y2, Y0 and Y1 coils are all OFF.
In the second cycle, the PLC scans the ladder diagram from top to bottom and from left to right. When scanning the Y0-1 contact, since Y0 was OFF in the previous cycle, the Y0-1 contact is still OFF, so Y2 is still OFF. When scanning the X0 contact branch, X0 in the input image register is already ON, so the Y0 coil is ON. At this time, the Y0-2 contact is ON. When scanning this branch, the Y1 coil is ON, but it has lagged behind X0 by one working cycle. In this cycle, since the Y0 coil is ON, the Y0-1 contact should also be ON in the output refresh stage. In the
third cycle, the scan is still from top to bottom and from left to right. Since the state of the Y0-1 contact in the element image register is already ON, when the scan reaches this branch during the program execution phase, Y2 is in the ON state, but at this time it has lagged behind X0 by two working cycles.
From the above analysis, it can be seen that the connection of the Y0 coil and the Y1 coil lags behind the connection of the X0 contact by one working cycle. The connection of the Y2 coil lags behind the connection of the X0 contact by two working cycles.
(2) Other reasons for the input/output response lag.
In addition, there are also the lag effect of the input filter circuit and the mechanical lag effect of the output relay, which affect the speed of time.

3 Conclusion

(1) PLC adopts a cyclic scanning working mode. When executing a program, even a ladder diagram that is consistent with the relay control circuit diagram may lead to different execution results. 
(2) In the scanning cycle, since the input signal is only read in the input stage, during the program execution stage, even if the input signal changes, the content of the input status table will not change, so no response can be obtained in this cycle. This is the hysteresis phenomenon of the PLC input/output response. The maximum lag time is 2 to 3 cycles, which is related to the programming method. However, this lag response is completely allowed in general industrial control systems. In some occasions where fast input and output are required, fast response modules, high-speed counting modules, and interrupt processing can be used to minimize the lag time. 