Design of Controller for Multi-channel Serial A/D Converter Based on FPGA

With the application and development of modern electronic technology, more and more electronic applications are changing from analog systems to digital systems. A/D converters are the interface between analog systems and digital systems, and they are responsible for converting analog signals into digital signals. In some multi-channel signal acquisition systems and real-time digital signal processing systems, the multi-channel expansion, high precision, low cost, and real-time performance of A/D conversion are becoming more and more important. In general signal acquisition systems, high-precision A/D converters are controlled by single-chip microcomputers or microcontrollers, and the method of software simulation of A/D converter timing is usually adopted. Therefore, the burden on the CPU is increased and the working efficiency of the CPU is reduced. In the multi-channel expansion application of multiple A/D converters, the real-time performance of signal acquisition is reduced.

Field Programmable Gate Array (FPGA) is a programmable logic device developed in the mid-1980s based on PAL, GAL and other logic devices. It is characterized by high integration, high speed and high reliability, and designers can modify the logic function of the device on site. VHDL (VHSIC Hardvcare Description Language) is one of the common hardware description languages ​​currently used to describe the input, output, and mutual behavior and function of a digital circuit.

The high integration and high speed of FPGA make it more suitable for sampling control of high-speed A/D devices than single-chip microcomputers and microcontrollers. This paper designs a controller of high-speed serial input/output A/D converter based on FPGA, which completes the sampling control of ADS7844 chip, improves the real-time performance of sampling and reduces the operating burden of the main CPU.

2 ADS7844 Function Introduction

ADS7844 is a high-performance, wide-voltage, low-power 12-bit serial digital-to-analog converter launched by Burr_Brown. It has 8 analog inputs and can be programmed as an 8-channel single-ended input A/D converter or a 4-channel differential input A/D converter by software. Its conversion rate is up to 200 kHz, and the maximum linear error and differential error are only ±1 LSB. ADS7844 can work normally with a power supply voltage between 2.7 and 5 V, with a maximum operating current of 1 mA and a power consumption of only 3 μA after entering the low-power state. ADS7844 communicates with the CPU through a 6-wire serial interface, and the interface is simple and convenient.

2.1 Pin Functions of ADS7844

CH0~CH7: analog input terminals. When the device is set to single-ended input, these pins can be connected to the signal ground to form an 8-channel single-ended input A/D converter. When the device is set to differential input, CH0-CH1, CH2-CH3, CH4-CH5, and CH6-CH7 can form a 4-channel differential input A/D converter.

COM: signal ground;

Vref: reference voltage input terminal, the maximum value is the power supply voltage;

CS: Chip select terminal, low level is valid, when this pin is high level, other digital interfaces are in three states;

Dclk: External clock input terminal, under the action of the clock, the CPU writes the control word into ADS7844 and reads the conversion result from it;

Din: Serial data input terminal, when the chip select is valid, the control word is locked into ADS7844 bit by bit at the rising edge of Dclk;

Dout: Serial data output terminal, when the chip select is valid, the conversion result is shifted out of ADS7844 bit by bit starting from the falling edge of DcIk;

BUSY: "Busy" signal output terminal, becomes low after receiving the first bit of the control word, and only when the conversion is completed and the chip select is valid, this pin outputs a high pulse;

SHDN: Power off terminal, low level is valid. When SHDN is low level, ADS7844 enters low power consumption state;

Vcc, GND: power supply and digital ground respectively.

2.2 ADS7844 control word and conversion timing

The control word of ADS7844 is described in Table 1.

The control word of ADS7844 has 8 bits, of which S is the start bit, and the start bit of the control word is always "1". A2~A0 are channel selection bits, corresponding to 8 channels in single-ended input, and for differential input, 000~011 correspond to CH0-CH1, CH2-CH3, CH4-CH5, CH6-CH7, and 100~111 correspond to CH0-CH1, CH1-CH0, CH3-CH2, CH5-CH4, CH7-CH6. Bit3 is not defined. SGL/DIF is the mode control bit. When this bit is "1", it is single-ended input mode, and when it is "0", it is differential input mode. PD1 and PD0 are power-off mode control bits. If it is "00", it means that ADS7844 automatically enters power-off mode when no data conversion is performed. If it is "11", the chip is always in power-on mode.

ADS7844 has multiple conversion timings, and the basic timing is shown in Figure 1.

As can be seen from Figure 1, a conversion cycle requires 24 clock cycles, 8 of which are used to input the control word and 16 are used to read the conversion result. All bits of the control word are locked into the chip at the rising edge of the clock, and the conversion result is shifted out one by one at the falling edge of the clock. All data shifted in and out are high-bit first and low-bit last. It should be noted that ADS7844 is a 12-bit A/D converter, and its conversion result is only 12 bits. Therefore, after shifting out the 12-bit result, 4 clocks need to be sent in to complete the entire conversion process. The data shifted out by these 4 extra clocks is "0" and should not be treated as the conversion result when used.

3 Design of ADS7844 controller

The interface circuit between the sampling controller AD_CONTROLLER and ADS7844 designed with FPGA is shown in Figure 2. The basic timing is as described above. The input clock of AD_CONTROLLER is 12 MHz, which is divided by 4 internally and output to the CLK pin of ADS7844. cs_all is the start signal from the CPU. When it is low, AD_CONTROLLER starts working. addr[3..0] is the corresponding channel address of ADS7844, and data[15..0] is the A/D conversion result of the channel corresponding to a certain address. When the conversion of a certain channel is completed, the oe signal changes from low level to high level and lasts for 1 cycle.

AD_CONTROLLER is mainly composed of a frequency division module (fq), an A/D conversion cycle forming module (fq_cs); an A/D converter chip select signal module (cs_pulse); a channel address and control word forming module (addr_1); an A/D conversion data output module (from_ad) and a control word shift output module (to_ad). Its structure is shown in Figure 3.

Take the FPGA operating frequency of 10 MHz, divide it by 4 to get 2.5 MHz as the clock of the A/D converter. The divider is usually implemented by a counter, which has been described in detail in various VHDL textbooks and will not be repeated here. The signal cs sends a high-level pulse of 1 clk1 cycle every 28 clk1 clock cycles and converts the analog input channel once. In 28 clk1 cycles, the A/D converter chip select cs_ad signal occupies 4 cycles, and the serial output of the control word (di) occupies 8 cycles. After the ADS7844 chip receives the control word from the Din pin, it starts to serially output the A/D converted data to the Dout pin at the falling edge of the next cycle. The from_ad module performs serial/parallel conversion and outputs (data[15..0]). This serial-to-parallel conversion requires 16 cycles. The falling edge of the signal stld latches the control word (control_word[7..0]) generated by the state machine into the parallel/serial shift register (74165) inside the to_ad module. After 8 cycles, the control word is input into the ADS7844 chip through the di pin. The generation of the cs pulse is realized by the counter, which will not be described in detail here. The cs_ad chip select signal is obtained by widening the cs signal by 2 cycles through the cs_ad module. Its circuit structure is as follows:

The circuit consists of a counter (cs_wide), a leading edge D flip-flop (inst6) and a trailing edge D flip-flop (inst3). When the cs signal rises, inst6 is triggered and cs_ad is set to a high level. After 2 cycles, inst3 is triggered by the falling edge and outputs a high level. After inversion, inst6 and the counter cs_wide are cleared, and cs_ad outputs a low level. It can be seen that the signal of cs_ad is obtained after the cs signal is widened by 2 cycles.

The channel address and control word formation module (addr_1) can realize various required input modes and generate channel addresses and control words. Taking the single-ended input mode as an example, the VHDL code is as follows:

Here, a dual-process finite state machine (FSM) is used to design the channel address generator. When addr <= "0000", it means no channel is selected and ADS7844 does not work; when addr <= "0000", it means channel 1 is selected, and so on.

4 Computer simulation analysis

Quartus Ⅱ 6.0 was used for analysis, synthesis and layout, occupying a total of 59 LEs (logic elements) of Altera cyclone FPGA. The waveform simulation is shown in Figure 5.

In Figure 5, the period of elk is 100 ns, clk1 is the working clock after the system clock is divided by 4, and when cs_all is low, AD_CONTROLLER starts working. The control word (10000100) generated by the state machine is latched into the shift register at the falling edge of stld, and when cs_ad changes from high to low, the control word is shifted out to the di port one by one. Here, it is assumed that when ADS7844 receives the control word and shifts out the converted data 1000000000010000 from the ad_do port one by one, after 16 cycles, oe changes from low to high, and the falling edge of oe can latch the data shifted into the register. As can be seen from Figure 5, the simulation waveform is consistent with the ADS78414 control waveform, achieving the design purpose.

5 Conclusion

This test is used for the battery voltage and current information collection part of the hybrid vehicle battery management system. The battery management system usually adopts a dual-chip microcomputer structure, one microcontroller completes the battery information collection function, and the other microcontroller completes the battery SoC (State of Charge) calculation and human-computer interaction function. This system structure is complex and the reliability is reduced. To solve this problem, the A/D controller is encapsulated into a custom IP core based on the Avalon bus and applied to the NIOS Ⅱ embedded system supported by Altera's FPGA. The NIOS Ⅱ soft-core CPU only reads the collected data in the interrupt service program caused by the A/D controller, which greatly improves the collection speed and CPU efficiency, allowing more CPU resources to be used for SoC calculation and human-computer interaction. This battery management system based on SoPC (Systemon Programmable Chip) has a compact structure, complete functions, and greatly improved reliability.

There are many advantages of using FPGA to design control circuits. FPGA can not only be programmed any number of times, but users can also use development tools to quickly program, compile, optimize, and simulate until the final chip is produced. High integration allows users to use hardware description languages ​​and development tools to implement various complex logic circuits and systems on chip on a single FPGA chip, improving system performance, reducing circuit area, and reducing costs. High speed effectively solves the contradiction between the accuracy of analog control and the speed of digital control. With the improvement of FPGA performance and the reduction of costs, FPGA-based digital circuits and SoPC (System on Programmable Chip) represent the development direction of embedded systems, and FPGA will be used more and more widely.