CCD image sensor TCD1206 structural features and pins

TCD1206 is a high-sensitivity, low dark current, 2,160-pixel dual-channel linear array CCD image sensor. The photosensitive element array is composed of 2,236 PN junction photodiodes, of which the first 64 and the last 12 are used for dark current detection and are shielded. The middle 2,160 photodiodes are exposure image-sensitive units. The size of each photosensitive unit is 14μm long and 14μm high, and the center distance is also 14μm. The total length of the photosensitive element array is 30.24 mm.

The main features of TCD1206 are: 1) The number of photosensitive pixels is 2160 pixels; 2) The pixel unit is: 14μmxl414μm (the center distance between adjacent pixels is 14μm); 3) The spectral range is 250~l100 nm: 4) The photosensitive area uses a high-sensitivity PN junction as a photosensitive unit; 5) The clock is two-phase (5 V); 6) The internal circuit includes a sample-and-hold circuit and an output pre-amplification circuit; 7) It uses a 22-pin DIP package.

The structural principle and pin function of TCD1206

Structural principle

TCD1206 is a dual-channel linear CCD with two-phase electrodes. Its structural principle is shown in Figure 1. The middle row is a photosensitive array composed of multiple photosensitive diodes, with an effective unit of 2,160 bits. Its function is to receive the light irradiated to the CCD silicon chip and convert it into a charge signal. On both sides of the photosensitive element are MOS capacitor columns that store its charge, a storage gate. On both sides of the MOS capacitor column are transfer gate electrodes SH. On both sides of the transfer gate are CCD analog shift registers, whose output part is composed of a signal output unit and a compensation unit.

Pin Function

The TCD1206 device uses a DIP package, and the functions of each pin are shown in Table 1.

Drive timing and drive design

Driver Timing Analysis

TCD1206 works under the driving pulse shown in Figure 2. When the SH pulse is at a high level, the φ1 pulse is at a high level, and a deep potential well is formed under it. At the same time, the high level of SH makes the deep potential well under the φ1 electrode communicate with the storage potential well of the MOS capacitor. The signal charge packet in the MOS capacitor is transferred to the potential well under the φ1 electrode of the analog shift register through the transfer gate. When φSH changes from high to low, the shallow potential well formed by the low level of φSH isolates the potential well under the storage gate from the potential well under the φ1 electrode. The storage gate potential well enters the light integration state, and the analog shift register will drive the signal charge transferred to the potential well under the φ1 electrode to shift to the left under the action of the φ1 and φ2 pulses, and output it from the OS electrode through the output circuit. The DOS terminal outputs the compensation signal.