Design of 16-channel adjustable speed colored light controller based on VHDL

0 Introduction
In recent years, FPGA/CPLD has developed rapidly. With the continuous advancement of integrated circuit manufacturing technology, cost-effective FPGA/CPLD devices have been introduced, making FPGA/CPLD an important way of hardware design today. Compared with traditional circuit design methods, FPGA/CPLD has powerful functions, short development cycle, low investment, easy tracking of market changes, timely modification of product design, and intelligent development tools. Among the many FPGA/CPLD design languages, VHDL language, as a mainstream hardware description language, has strong circuit description and modeling capabilities. It can model and describe digital systems from multiple levels, thereby greatly simplifying hardware design tasks, improving design efficiency and reliability, and showing strong vitality and application potential in terms of language readability and hierarchical and structured design.
QuartusⅡ is an FPGA/CPLD integrated development environment launched by Altera in the early 21st century. It is an updated product of Altera's previous generation FPGA/CPLD integrated development environment Max+PlusⅡ. It has a friendly interface, is easy to use, and has powerful functions. It provides designers with a design environment that is independent of structure, allowing designers to easily input designs, quickly process and program devices.
In this paper, under the QuartusⅡ development environment, a color light controller with 4 color light change modes and adjustable change speed is designed using VHDL language.

1 Design ideas of 16-channel adjustable color light controller
The 16-channel adjustable color light controller can be divided into three parts according to its function, as shown in Figure 1. Among them, the 8 Hz frequency division part is used to divide the clock signal with a frequency of 10 MHz to obtain a clock signal CLK8 with a frequency of 8 Hz. CLK8 is used as the reference clock of the speed control part. Through counting and frequency division, clock signals with frequencies of 4 Hz, 2 Hz and 1 Hz can be obtained. Then one of them is selected as the color light clock signal CLKQ by the speed regulation signal. CLKQ is the reference clock of the color light control part, which is used to determine the speed of the color light change. In this way, the speed regulation signal SPD can control the speed of the color light change, making the color light speed adjustable.

The colored light control part controls 16 colored lights by outputting a 16-bit binary number (i.e., the colored light output signal Q). Each bit of the binary number corresponds to the switch of a colored light. When the digit is "1", the light is on, and when the digit is "0", the light is off. There are 4 modes for the transformation of colored lights:
s0 mode: only 1 light is turned on, and it moves from the leftmost end to the rightmost end one by one, that is, the output signal Q moves 1 "1" to the 0th bit in sequence starting from the 15th bit;
s1 mode: only 1 light is turned on, and it moves from the rightmost end to the leftmost end one by one, that is, the output signal Q moves 1 "1" to the 15th bit in sequence starting from the 0th bit;
s2 mode: 2 lights are turned on, and they move from the left and right ends to the middle at the same time, that is, the output signal Q moves 1 "1" from the 15th bit to the 8th bit in sequence, and at the same time, it moves 1 "1" from the 0th bit to the 7th bit in sequence;
s3 mode: 2 lights are turned on, and they move from the middle to the left and right ends at the same time, that is, the output signal Q moves 1 "1" from the 8th bit to the 15th bit in sequence starting from the 7th bit, and at the same time, it moves 1 "1" to the 0th bit in sequence.
The four modes cycle in sequence. If the reset signal RST input is high, the cycle is interrupted, the output signal Q is set to zero, and all the colored lights are off. After RST returns to a low level, the cycle starts again from the sO mode.

2 Implementation of 16-channel adjustable speed colored light controller
The circuit symbol of the 16-channel adjustable speed colored light controller designed in this paper is shown in Figure 2, where clk is the 10 MHz clock signal input terminal, rst is the reset control terminal, spd is the speed control signal input terminal, and q is the colored light control signal output terminal.

The VHDL code of the 16-channel adjustable speed colored light controller designed in this article is as follows:

It is worth noting that the 16-channel adjustable speed colored light controller designed in this paper uses a data loop algorithm, which is simpler than the previous case when statement and has more powerful functions. It has the following characteristics:
(1) During hardware verification, the pin of the speed control end SPD is connected to the DIP switch to realize manual control of the speed of the colored light change. In further design, the internal control of the SPD signal can also be used to realize automatic adjustment of various change speeds.
(2) The design uses data shifting to realize the change of colored lights, which is more conducive to the expansion of the color light change mode. Although this design only designs 4 change modes, it can be easily expanded to 6 to 8 modes or even more as needed.
(3) The division ratio of the 8 Hz frequency division part is very large and is not suitable for computer simulation verification. The division ratio needs to be reduced during simulation and restored to a larger division ratio during hardware verification.

3 Analysis of simulation results
The 16-channel adjustable speed colored light controller designed in this paper was simulated and verified in the QuartusⅡ development environment. The simulation waveform is shown in Figure 3. The simulation results are analyzed as follows:

(1) clk is the clock signal, and the rising edge of the clock signal triggers the divider counting;
(2) rst is the reset signal input terminal. When it is high level, the color light control output signal q is cleared. After rst returns to low level, the color light control output signal q restarts the cycle from the so mode;
(3) spd is the speed regulation signal input terminal. Corresponding to the four values ​​of spd "00", "01", "10", and "11", the speed of the color light change is 1 Hz, 2 Hz, 4 Hz, and 8 Hz respectively;
(4) q is the color light control signal output terminal. As shown in Figure 3, this design successfully realizes the cycle of four transformation modes and the adjustment of various transformation speeds.

4 Conclusion
After the designed 16-way adjustable speed colored light controller was simulated and verified in the QuartusⅡ development environment, it was downloaded to the ZYllEDAl3BE experimental box of Hubei Zhongyou Technology Industry Co., Ltd. for hardware verification. The experimental box uses the ACEXlK series EP1K30QC208 chip as the core chip. The experiment proves that the design is correct, the functions are complete, and the operation is stable. In addition, the 16-way adjustable speed colored light controller designed in this paper can add more transformation modes as needed to make the colored lights more colorful.