Design of Intelligent Temperature Controller for Air Conditioner Based on SOPC

1 Introduction

Intelligent control is an emerging research field in the control field and a marginal cross-disciplinary subject. One definition of intelligent control is: the application of artificial intelligence theory and technology and operations research optimization methods combined with control theory methods and technologies to emulate human intelligence in an unknown environment to achieve system control. All major chip manufacturers in the microelectronics technology industry have launched dedicated neural network chips and fuzzy chips. The use of such high-speed dedicated chips has greatly facilitated the implementation of intelligent control application systems. This paper uses field programmable gate array (FPGA) technology to study the design and implementation of intelligent controllers.

2 Controller Hardware Design

The controller main chip adopts the APEX series FPGA chip of ALTERA, and the chip model is EP20K200EFC484-2X. The APEX20K series device is a PLD device series with a multi-core structure, supporting programmable single-chip system SOPC. This model has 200,000 available gate resources, 13KB of internal storage space, 382 user-available pins, and 1.8V/2.5VI/O. The main processor adopts ALTERA's 32-bit NIOS processor soft core, the system bus adopts AVALON bus, and the peripheral expansion includes on-chip memory (9KB), RS232 serial communication port, intelligent control algorithm accelerator unit, analog input port, digital/switch output port, keyboard PIO, LED display PIO, etc. The hardware architecture block diagram is shown in Figure 1.

Figure 1 Hardware architecture

2.1 Nios soft-core processor

NIOS CPU is a pipelined, single instruction stream RISC processor with separate instruction and data memory ports (Harvard memory architecture). The processor in this paper has a main frequency of 33.333MHz. The internal registers in NIOS CPU include: a general register file, multiple internal control registers, a program counter, and a K register for prefix instructions.

NIOS3.0 CPU allows users to cancel support for trap instructions, hard interrupts or internal exceptions to configure the NIOS system into a simplest control system (not running complex software). The NIOS processor has an optional on-chip JTAG debug module for communication between the debug tool and the NIOS CPU. The debug module contains an IP core designed by First Silicon Solution (FS2). In the NIOS CPU, this debug module is called the NIOS OCI debug module. The NIOS OCI debug module can implement run control, hardware breakpoints and software tracing.

2.2 UART serial communication

The UART peripheral hardware circuit calls the NIOS system IP library module integrated into the development environment by ALTERA, and its functions are described as follows. NIOS UART is used to implement simple RS-232 asynchronous transmission and reception logic in Altera's FPGA. UART sends and receives serial port data through two external pins (TxD and RxD). In order to match the voltage signal of RS232, a level conversion chip is required between the RxD/TxD input and output pins and the corresponding external RS232 connection.

The UART transmit logic contains a 7-bit, 8-bit, or 9-bit txdata holding register. The transmit shift register is directly connected to the TxD data pin, and the data is shifted out to TxD LSB first. The transmit logic can automatically insert the correct start bit, stop bit, and parity bit in the continuous TxD data stream according to the RS232 communication protocol. The UART receive logic contains a 7-bit, 8-bit, or 9-bit receive shift register and a 7-bit, 8-bit, or 9-bit rxdata holding register. The rxdata holding register can be read directly by software. The receive logic automatically detects the correct start bit, stop bit, and parity bit in the continuous RxD data stream according to the RS232 communication protocol.

UART generates an IRQ output signal as part of its Avalon bus interface. When one or more internal conditions occur and the corresponding interrupt enable bit of the control register is also 1, UART issues an interrupt request. At reset, all interrupt enable bits are set to 0. Therefore, UART can only issue an interrupt request when software sets one or more interrupt enable bits to 1. The UART module and bus interface are shown in Figure 2. Among them, address is the relative address, irq is the interrupt request signal, chipselect is the chip select signal, dataavaliable is the valid signal of the receive data line, readyfordata is the signal that the receive data word is ready, and begintransfer is the signal to start sending data.

Figure 2 UART module and bus interface diagram

2.3 AVALON bus and user-defined logic control algorithm module

The AVALON bus is mainly used to connect the on-chip processor and peripherals to form a programmable system on a chip (SOPC). It describes the port connection relationship between the master and slave components, as well as the timing relationship of communication between components. The AVALON bus has multiple transmission modes to adapt to the requirements of different peripherals. The basic transmission mode of the AVALON bus is to transfer a single byte, half word or word between a master peripheral and a slave peripheral. When a transmission is completed, the AVALON bus can always start another transmission immediately in the next clock cycle regardless of whether the new transmission process is still between the same peripherals. The AVALON bus supports multiple bus master peripherals, allowing multiple data units to be transferred between peripherals in a single bus transaction. This multi-master device structure provides great flexibility for building SOPC systems and can adapt to high-bandwidth peripherals. The AVALON bus is designed for the SOPC environment, and the interconnection logic is composed of logic units inside the PLD.

AVALON bus also includes many other features and conventions to support SOPC Builder software to automatically generate systems, buses and peripherals, such as a maximum address space of 4GB, built-in address decoding, multi-master bus structure, wizards to help users configure the system, dynamic address alignment, etc.

In order to realize fast real-time system, the controller neural network control algorithm is implemented by hardware circuit, which is connected to the system bus as a user-defined IP component in the form of a peripheral algorithm accelerator. The parallel input and output (PIO) module is a 1 to 32-bit parallel input/output module. PIO is used as a memory image interface between the software and the user-defined logic. The control word controls the operation of the algorithm module. Status word 0 indicates that the control algorithm module is running, status word 1 indicates whether there is a new input in the input register, and status word 2 indicates that there is a new output in the output register. When the controller has a new output result, it is set to high. The input register contains the user temperature set value and the detected system output value. The software can write to the register and set the status word 1 high at the same time; the output register is the control output, and the software can read its value and set the status word 2 low at the same time.

2.4 Timer

SOPC Builder can automatically generate the source code of the timer module and the corresponding software interface subroutine, which is convenient for system integration. The NIOS timer module is a 32-bit internal timer. The software can operate the timer by writing control registers and read the internal counter value. The timer module can generate interrupt request signals and can also use internal control bits for interrupt masking.

Software can control the timer in the following ways: preset the periodl and periodh registers to set the timer period, set the start and stop bits of the control register to enable or disable interrupts, set the ito bit of the control register to enable or disable interrupts, and set the timer's operating mode (timer or counter) by setting the cont bit in the control register. The NIOS timer is driven by the system main clock (clk), which is also used by the NIOS CPU and other peripherals. This clock drives both the software interface registers and the internal counters.

3 Controller Software Design

In the SOPC Builder development tool, set the properties of each hardware module, assign physical addresses, configure the size of storage space, and generate the hardware system. Then develop the software application and write software drivers for each peripheral module.

1. Control command input subroutine

Field control command input uses 6 buttons to simulate remote control input.

The key input uses an interrupt response mechanism. The NIOS processor interrupt mechanism allows up to 64 exceptions, including external hardware interrupt sources, internal exception sources, and direct software exceptions. The key interrupt service program completes the reading of the new command status word (6 bits) into the command buffer and sets the new command status bit to high.

2.Serial communication interface subroutine

The serial communication adopts the interrupt response mechanism. The interrupt service program completes the detection of the data packet header, the reception and verification of the data packet, and sets the reception flag of the new data packet to high. The serial port data packet decoding subroutine removes the header and tail of the packet, interprets the command code, and executes the corresponding processing program. This subroutine test is carried out on the experimental board to realize the serial port communication with the PC. The experimental process is to send a group of data packets from the serial port debugger software on the PC to the experimental board. The system on the experimental board receives the data packet and verifies and interprets it. If the verification code is correct, the data is packaged and the checksum is added and sent to the PC.

3. Controller application design

The controller top-level software application flow chart is shown in Figure 3.

Figure 3 Application software flow chart

Initialization completes the temperature setting value, displays the register setting initial value and other tasks, and the equipment detection completes the detection of whether each peripheral is intact, otherwise an error signal is issued. Next, check the new key status bit to see if there is a new key command input, if so, call the key processing subroutine, otherwise continue to check whether there is new data input from the serial port, if so, call the serial port data processing subroutine, otherwise enter the A/D acquisition program, compare the collected field temperature value with the given value, if the difference is not within the allowable range, call the intelligent algorithm module, otherwise return.

The author's innovation

The research in this paper shows that it is an effective means to realize intelligent controller based on field programmable gate array (FPGA). This paper designs an intelligent controller for air conditioner temperature based on SOPC. The intelligent control algorithm module is connected to SOPC as a user-defined logic unit, and expands the functions of human-machine interface, communication interface, data channel, etc. to form a controller with certain versatility. The research shows that SOPC is a flexible and effective way to realize intelligent controller.