Design and implementation of a new type of PID controlled all-digital phase-locked loop

The phase-locked loop is a closed-loop automatic control system that can track the phase of the input signal. It is widely used in signal processing, clock synchronization, frequency multiplication, frequency synthesis and other fields. It adjusts the output frequency of the voltage-controlled oscillator according to the phase difference between the input signal and the feedback signal, and finally achieves that the input signal frequency is equal to the output signal frequency, and the input signal and the output signal maintain a constant phase difference.
The traditional PI controller can eliminate the steady-state error and ensure the locking accuracy, but it has an adverse effect on the damping. Introducing the differential term in the PI controller can improve the response speed and damping, and ensure the locking time, but it cannot reduce the steady-state error. Therefore, this paper proposes an integral separation PID control, which can greatly improve the response time and damping and reduce the steady-state error, thereby ensuring the phase-locking accuracy and phase-locking time.
1 Circuit structure and working principle
1.1 Fully digital phase-locked loop circuit structure
The system block diagram of the fast full-digital phase-locked loop is shown in Figure 1.

The phase detector uses a JK trigger. The phase detector has a simple structure and a phase detection range of ±π, which can meet the needs of general engineering. Since the phase detector outputs binary high and low pulses, a digital filter is required to smooth the fluctuations and eliminate the influence of noise and interference pulses. There are two general digital sequence filters: N before M sequence filter and random wandering filter. The digital filter is not a loop filter. It is inert. It does not affect the order of the loop when added to the loop. It only plays the role of filtering noise and resisting interference. This paper uses a random wandering filter. The loop filter uses a PID controller, which can well control the speed and accuracy of the loop phase correction. Compared with the PI controller in the literature [1], it has better characteristics. The digital voltage-controlled oscillator uses a variable modulus divider. The M divider divides the output signal so that the loop obtains the corresponding multiplied frequency signal.
1.2 Circuit working principle
The phase detector compares the phase difference between the input signal and the output signal to generate an error high and low level pulse sequence pha. The width of the pulse is proportional to the phase error of the input and output signals. The K-sequence filter quantizes the phase error signal and eliminates the influence of input signal noise and interference pulses. When pha is high, the K-sequence filter counts up fO. When the counter overflows, it generates an addition pulse i to the loop filter, and resets the counter and counts again. On the contrary, when pha is low, the K-sequence filter counts down fO. When the counter is reduced to zero, it generates a subtraction pulse d to the loop filter, and resets the counter and counts again. In one pha cycle, the K-sequence filter generates a comprehensive value of addition and subtraction pulses, which characterizes the magnitude of the phase error between the input signal and the output signal. Since the influence of interference and noise is random, the probability of the addition and subtraction pulses generated by the K counter is equal at this time, so the loop has a strong anti-interference ability. The loop filter adopts PID control, so the signal output by the digital voltage-controlled oscillator is fed back to the loop filter as a sampling signal after M frequency division. The loop filter counts and synthesizes the number of addition and subtraction pulses generated by the K counter in a pha cycle at its rising edge, performs PID calculation, and outputs the count value to the voltage-controlled oscillator as a frequency division factor and register clearing operation. In the control process, since the signal M output by the voltage-controlled oscillator is used as the sampling signal of the loop filter, the sampling cycle and the cycle of the output signal fout are synchronized, which not only ensures cycle-by-cycle control, but also ensures that a new frequency division count value is assigned to the register of the voltage-controlled oscillator when the counting starts.
2 System structure and performance analysis
2.1 Mathematical model analysis
Figure 2 is the mathematical model of the fully digital phase-locked loop in Figure 1.

From the analysis of the PI controller and the closed-loop response of the system in the literature [1], it can be obtained that the PI control phase-locked loop can make the control meet the overshoot, adjustment time and zero steady-state error, and the natural resonant frequency is proportional to the frequency of the input signal. However, if a faster response speed is required without increasing the overshoot, a differential term should be added to the controller, that is, PID control. In traditional PI control, due to the existence of the integral term, although static error can be eliminated and accuracy can be improved. However, when the process starts, ends, or the set value is greatly increased or decreased, the system will output a large deviation in a short period of time, which will cause the integral accumulation of the PI operation, and eventually cause a large overshoot of the system, and even cause system oscillation. Therefore, this paper adopts the integral separation PID control algorithm, which not only maintains the integral effect, but also reduces the overshoot, so that the control performance has been greatly improved. The specific implementation is as follows:

The simulation diagram of the integral separation PID algorithm is shown in Figure 3.

2.2 Loop Linearity Analysis
When the phase-locked loop fluctuates near the locking point, the change in the count value N is small. Assuming that the loop is a second-order loop at this time, the transfer function of the voltage-controlled oscillator is:



It can be seen from equations (7) and (8) that as long as the count value k, integral coefficient ki, and proportional coefficient kp of the K-sequence filter are obtained, the resonant frequency and damping coefficient of the loop can be obtained, and vice versa. In addition, observing the natural resonant frequency, it can be found that it is proportional to the frequency of the input signal, which means that the tracking speed of the phase-locked loop is proportional to the frequency of the input signal.
The general steps of PID parameter engineering tuning are:
(1) Only add the proportional control link and slowly increase kp to make the system oscillate slightly.
(2) Add the differential control link and slowly reduce kd, which is equivalent to increasing the damping of the system to stabilize the system.
(3) After the system stabilizes, increase kp again to make the system oscillate slightly, and then reduce kd to stabilize the system. Repeat this process until both kp and kd cannot change.
(4) Reduce the value of kp appropriately, add an integral control link, and slowly increase the value of ki until the steady-state error is within an acceptable range.
(5) In order to make the system more reliable and stable, ensure robustness. Finally, the values ​​of kp, kd, and ki should be appropriately reduced, and then some corresponding adjustments should be made based on experience.
3 System Simulation Analysis
3.1 Simulation Results
This design is designed using VHDL language, Quartus software is used as the design platform, and CycloneII EP2C35F484C8 device is used to complete the design.
In this design, all parameters are integers, and ki=2, kp=2, kd=4 are selected. The modulus of the K sequence filter is 36, and the M division ratio is 1. The system simulation diagram when the phase step is 180 is shown in Figure 4.

3.2 Result Analysis
After repeatedly adjusting the system parameter K value, a better K value was selected as the modulus value of the sequence filter, and ki=2, kp=2, kd=4 were selected as the integral coefficient, proportional coefficient and differential coefficient of PID. It can be seen from the simulation diagram that the design structure can achieve the locked state, and the locking time is reduced, achieving the expected effect.
This paper proposes a new loop filter, which uses an integral separation PID controller as a loop filter, effectively reducing the locking time and improving the locking accuracy. The phase-locked loop has strong versatility, and the circuit parameters are easy to configure, the design is simple, and the integration is high. Theoretical analysis, simulation and experimental results all show that the fully digital phase-locked loop has good performance. It is implemented using FPGA, which occupies less resources and is easy to make into a system-on-chip SoC.
References
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