DSP+CPLD Space Transient Optical Radiation Signal Real-time Detection System

The detection system performs real-time recognition and processing of the input spatial transient light radiation signal, inversely estimates the energy of the spatial transient signal and reports the time of occurrence. The digital processing solution of DSP+CPLD is adopted, and the high-speed digital signal processing characteristics of DSP and the complex logic programmable characteristics of COLD are utilized to realize real-time recognition and processing of transient signals. Among them, CPLD is used to realize A/D variable rate sampling, which solves the contradiction between the limited area of ​​the embedded system circuit board and the large-capacity storage space required for real-time processing.

Real-time processing of space transient optical radiation signal detection systems in my country, there are many old models, most of which are not equipped with automatic detection and recording equipment. The recording, data processing and reporting of space transient signals are mostly done manually, which is difficult to meet the requirements of fast and accurate signal recording and meteorological information network access in complex environments. In order to meet the requirements of modern meteorological analysis, the use of DSP+CPLD will greatly improve the automatic recording and analysis capabilities of existing space transient signal detection.

In real-time signal processing technology, DSP+CPLD is a common method in the world. For example, the United States and Russia often use this method. DSP is a programmable digital microprocessor. Compared with single-chip microcomputers, DSP chips have software and hardware resources that are more suitable for digital signal processing and can be used for complex digital signal processing algorithms. This article uses the TM320C32 floating-point DSP chip of the American TI company's TM320C3x series as the host of the entire system, and uses it to complete the system control and digital signal processing functions.

cpld is a multi-purpose, high-density complex programmable logic device that can integrate part or all of the system's functions on a single chip. It is easy to design and modify, which can greatly shorten the development time and reduce the complexity of the system hardware. This article uses the cpld chip epm7128slc84 from altera's max7000s series to implement a/d variable rate sampling and other logic control.

1 System composition and basic principles

This detection system mainly solves the contradiction between the limited area of ​​the embedded system circuit board and the large amount of storage space required for real-time data processing, and realizes real-time signal processing.

The real-time detection system of space transient optical radiation signals is mainly composed of three modules: pre-processing circuit module, A/D variable rate sampling module, and DSP signal recognition and storage module.

The main functions of each module are:

(1) Pre-processing circuit module, responsible for tasks such as photoelectric conversion, background subtraction, and dynamic range compression of spatial transient light radiation signals;

(2) A/D variable rate sampling module, responsible for trigger signal generation, initial rise rate judgment, signal acquisition timing control, A/D variable rate sampling and FIFO buffer storage;

(3) DSP signal recognition and storage module is responsible for the rapid recognition and processing of spatial transient signals, inversion calculation of energy size, reporting the time of event occurrence and storing and transmitting data; at the same time, it controls the entire system and transmits data to a PC or other system.

2 Pre-processing circuit module

2.1 Photoelectric conversion

Since the spatial transient light radiation signal has a fast speed and a large dynamic range, the requirements for light radiation detectors are relatively high. This paper uses the S2387-1010R silicon photodiode from Hamamatsu Corporation of Japan, which has the characteristics of high sensitivity, large dynamic range, fast time response and large coverage.

2.2 Background subtraction

The energy of sunlight radiation is several orders of magnitude higher than that of transient light radiation signals in space. For the system, due to the influence of sunlight, the target signal is very weak and mostly buried in strong noise. Therefore, it is necessary to subtract the strong background signal to extract the useful target event transient signal.

In the automatic signal processing and analysis technology, the extraction of weak signals under strong background is a difficult point. Based on the characteristics that the background signal changes slowly while the target signal changes quickly, this paper uses a high-pass filter to subtract the background of the signal.

The high-pass filter can be realized by digital circuit or analog circuit. In order to simplify the circuit and reduce the pressure of subsequent processing circuit, this paper uses capacitors and resistors to build an analog high-pass filter for background subtraction.

The transfer function of the filter is:

h(s)=r/[(1/sc)+r]=src/(1+src)

By selecting appropriate resistance and capacitance values, the background subtraction of the target signal can be achieved.

2.3 Dynamic Range Compression

The dynamic range of spatial transient light radiation signals is too large. If A/D conversion is performed directly on them, the quantization resolution of A/D must be at least 15 bits. The large number of bits increases the amount of data for post-stage digital signal processing and reduces the real-time performance of the system. Therefore, a logarithmic amplifier is used to logarithmically compress the dynamic range of the signal. A 12-bit A/D converter can meet the requirements, reduce the amount of data processed, and improve the real-time performance of the system. This article uses the TL441M logarithmic amplifier from TI, USA. It is a single-chip high-performance logarithmic amplifier chip cascaded from four 30db logarithmic amplifiers, which can obtain an input voltage dynamic range of 120db.

3 A/D variable rate sampling module

3.1 Threshold Trigger

After pre-processing, the target signal enters the voltage comparator in the threshold trigger circuit. The DSP sets the threshold signal, which is latched and output to the voltage comparator through D/A conversion to be compared with the input target signal: if the target signal exceeds the threshold signal, a trigger signal is generated to drive the timing control circuit and the A/D conversion circuit to work; otherwise, it does not work.

3.2 CPLD controls A/D variable rate sampling

In order to further reduce the amount of data for signal processing and achieve real-time processing, this paper adopts the variable rate sampling method to solve the contradiction between the limited circuit board area and the large capacity storage space required for data processing.

From the characteristics of spatial transient light radiation signals, we can see that the initial value changes quickly, and the high-frequency component accounts for a large proportion; while the signal changes gradually decreases, and the later the signal is, the closer it is to the slowly varying signal, and the low-frequency content is high. Therefore, the method of gradually increasing the sampling interval is used to achieve variable rate sampling.

The initial sampling frequency is f, and the sampling frequency is reduced by half every m sampling points until the sampling is completed. The method used in the circuit implementation is: the A/D converter converts analog to digital quantity at a fixed conversion rate, and the CPLD controls the variable rate of sampling data to receive and store it in the FIFO.

The data stored in fifo is determined by its write enable control signal wen (active at low level): when wen is low, data is written into fifo at the rising edge of each write clock signal wclk; when wen is high, the data remains unchanged. Therefore, controlling the fifo variable rate to receive data is to control its write enable signal wen to change at intervals of low level. In CPLD, the timing signal of wen can be realized by dividing the write clock signal wclk by two every m points and adjusting the duty cycle.

The logic control of CPLD on the variable rate receiving sampling data of FIFO can be realized by three methods using the software MUX+PLUS II of Altera Corporation of the United States: one is to draw a circuit diagram using counters, frequency dividers, etc.; the second is to program using VHDL language or AHDL language; the third is to input timing waveform files. For this system, the second method is adopted. The A/D converter in this article adopts the AD678 of the American AD company. It is a 12-bit multi-purpose A/D converter, which includes a sample-and-hold, a microprocessor interface, a reference voltage source and a clock drive circuit, and has the characteristics of high reliability and low power consumption.

3.3 Preliminary judgment of ascent rate by cpld

The rising rate of the target signal amplitude value from the starting point of exceeding the threshold is an important criterion for judging its energy range. Therefore, the circuit uses cpld to make a preliminary judgment on the A/D sampling data. When the rising rate of the target signal meets the set requirements, a rising rate trigger signal is generated and a compliance judgment is made with other results; otherwise, the current data is discarded and the next detection data is waited for.

3.4 FIFO Storage

FIFO (first in first out) is a first-in first-out memory, that is, the data read in first is read out first. The access time of FIFO memory itself is generally tens of nanoseconds. The speed of peripherals such as A/D converters is generally slower than DSP. If FIFO is used, A/D can send data to FIFO first, and once FIFO is full, FIFO will request interrupt from DSP. This can save DSP waiting and query time, and the number of interrupts can also be reduced, thereby increasing transmission speed.

In this system, the fifo is used as a buffer memory to provide data to the rising rate initial judgment circuit and the DSP processor, and at the same time as a temporary storage unit for the variable rate sampling results. This paper uses the idt72xxx series synchronous parallel fifo of the American idt company to realize the data cache.

4 DSP signal recognition and storage module

4.1 DSP processing and storage

The core of the target signal automatic identification energy range and admission is the DSP signal processing module. In order to meet the requirements of real-time processing, the selection of hardware should be based on occupying as little system time resources as possible. Based on this basic principle, TMS320C32 is used as the processor. It is a chip with a high cost performance in the current TI company's floating-point DSP series and has been widely used in China. Its instruction cycle is 33/40/50ns, and it has rich hardware resources, such as 512 bytes of internal RAM, serial port, separate program bus, data bus and DMA bus, etc., and the external memory width is variable and has a program boot (boot-load) function. In terms of software, its rich instruction system, flexible program control, pipeline operation and various addressing modes make it particularly suitable for digital signal processing.

The DSP processing module is mainly composed of DSP, slow EPROM, high-speed SRAM, absolute clock chip RTC (real-time-clock) and RS232 serial port. Among them, the slow EPROM is mainly selected to reduce the system cost. This paper adopts the AT27C010 chip of Atmel Company in the United States. It is used to store programs and initialize data. High-speed SRAM is used for program execution and temporary storage of data. This paper adopts the IS61C6416 chip of ISSI Company in the United States. It cooperates with the slow EPROM to reduce the system cost and enable the program to run quickly, realizing real-time processing of signals.

Once the target event occurs, the input signal is converted by A/D and the data is cached in FIFO for DSP to call. After the DSP is powered on and reset, the program stored in the slow EPROM is loaded into the high-speed SRAM for operation, and the energy range of the target signal data temporarily stored in the FIFO is identified and processed; then the time value of the target event is obtained from the absolute clock chip RTC, and stored in SRAM together with the processing result; and the signal processing result and the time value of occurrence are output to the PC through the RS232 serial port.

The system workflow is: the spatial transient light radiation signal is converted into an electrical signal by the light radiation detector, and is amplified, denoised and compressed by the pre-processing circuit; if the signal exceeds the threshold, the threshold trigger circuit triggers the A/D sampling and temporarily stores it in the FIFO, otherwise the A/D is not triggered; the rising rate initial judgment circuit preliminarily detects the rising rate of the initial value of the signal? When the rising rate meets the set requirements, a rising rate trigger signal is generated, otherwise the current data is discarded; after the rising rate trigger signal is generated, the DSP obtains data from the FIFO, performs pattern recognition and processing on the signal, stores the processing results and transmits them to the PC through the interface circuit.

4.2 Absolute clock chip rtc

The so-called absolute clock refers to a permanent clock circuit that not only supports the update of daily time, but also supports the update of date (century, year, day, week). This article uses the ds12887 clock chip of the American Motorala company, which automatically records the year, month, day, hour, minute, second, and week. It contains 114 bytes of RAM unit and built-in crystal oscillator circuit, supports multiple interrupt modes, and the backup battery can work for 10 years. It is the mainstream real-time clock chip on computers.

4.3 RS232 serial port

Since the RS232 serial port level standard uses negative logic, which is incompatible with the DSP level standard, the data sent and received via the RS232 serial port needs to be level converted. This article uses the Maxim Corporation's MAX232 chip as a level conversion device, which only requires a +5V power supply, and the ±10V power supply required for level conversion is generated by the on-chip charge pump.

The serial port of DSP chip is synchronous serial port, while RS232 signal is asynchronous signal, so it needs to add asynchronous serial communication interface chip UART (universal asynchronous receiver/transmitter). This paper adopts TL16C550 chip of TI company, which has full-duplex, double-buffer transmitter and receiver. UART receives the processing result and occurrence time value sent by DSP, stores them in its own FIFO, and then converts the level through MAX232, and finally outputs them from RS232 serial port to PC.

This system uses DSP+CPLD mode to realize real-time processing of spatial transient optical radiation signals, effectively solving the contradiction between limited circuit board area and large-capacity storage space required for real-time processing, thus achieving the best cost-effectiveness of the system. Experiments show that the system can identify general spatial transient signals with relatively ideal results.