SVPWM Control Strategy and Experimental Study of Three-Level Inverter

Abstract: Based on the conventional two-level space vector PWM algorithm, a three-level space vector PWM algorithm is given, and an improved three-level space vector PWM modulation strategy is proposed to control the diode clamped three-level inverter, thereby achieving minimum switching loss. The digital control of the three-level inverter system is realized based on the TMS320F240 DSP, and the experimental results demonstrate the feasibility of the scheme.

Keywords: diode-clamped three-level inverter; space vector pulse width modulation; minimum switching loss; digital control

SVPWM Control Strategy and Experiment Research on Three-level Inverters

ZHANG Jie, ZOU Yun-ping, ZHANG Xian, DING Kai

Abstract:A novel space vector PWM (SVPWM) modulation strategy used in three- level NPC inverter to reduce switching loss is provided.Through coordinating transformation, it can easily obtain the control of the space voltage vector. The whole system has been implemented digitally by using TMS320F240 DSP, and the modulation strategy and control scheme is demonstrated by the experimental waveforms and corresponding spectrums.

Keywords:Diode-clamped three-level inverter; Space vector PWM (SVPWM); Least switching loss; Digital control

1 Introduction

In recent years, a new type of inverter, the multi-level inverter, has attracted more and more attention in the field of high-voltage and high-power applications. The idea of ​​the multi-level inverter was first proposed by Nabae in the early 1980s. Its basic principle is to synthesize a step wave voltage close to a sinusoidal output through multiple DC levels. The diode-clamped multi-level inverter discussed in this article divides the high voltage on the DC side into a series of lower DC voltages through series capacitors, and limits the reverse voltage borne by the switching device to the voltage of each capacitor through the clamping effect of the diode, thereby relatively increasing the inverter output voltage without increasing the device voltage level.

2 Topology

Although there are many types of multi-level topologies, they can be roughly divided into three types: diode clamped type, flying capacitor type and independent DC power supply cascade multi-level. These three multi-level topologies have their own advantages and disadvantages, among which the most widely used is the diode clamped multi-level topology. The research object of this paper is mainly the diode clamped three-level inverter. In the diode clamped three-level inverter shown in Figure 1, relative to the reference potential 0 of the midpoint of the DC side of the inverter, the output voltage of the inverter has a third level value of 0 in addition to the two-level inverter output voltage +UD/2 and -UD/2. In Figure 1, 12 turn-off power devices and 6 clamping diodes are used. Two capacitors of equal capacitance are connected on the DC side, namely C1 and C2. The voltage shared by each capacitor is UD/2, and through the clamping effect of the clamping diode, the voltage on each switching device is limited to a capacitor voltage (UD/2), thereby greatly reducing the voltage stress of the switching device.

Figure 1 Diode-clamped three-level inverter

Similar to the three-phase two-level inverter, the three-phase three-level inverter can also use switch variables Sa, Sb, and Sc to represent the switch state of each bridge arm respectively. The difference is that the A, B, and C bridge arms have three switch states respectively, so Sa, Sb, and Sc are three-state switch variables, as listed in Table 1.

Table 1 Three-level (NPC) inverter A phase switch status

Therefore, the voltage uAO of the A-phase output terminal A to the power supply midpoint 0 can be expressed by the A-phase switch variable Sa combined with the input DC voltage UD

uAO= ·UD (1)

The output line voltage can be expressed as

uAB=uAO－uBO= UD·(Sa－Sb) (2)

Arrangement is

= OUT· · (3)

Similar to the three-phase two-level inverter, the three-phase three-level inverter can define the switching state of the inverter as (SaSbSc), then the three-level inverter has 27 switching states, corresponding to 19 specific space voltage vectors, as shown in Figure 2, and the entire vector space is divided into 24 sectors. As can be seen from Figure 2, the 19 space voltage vectors can be divided into long vectors, medium vectors, short vectors and zero vectors, corresponding to 1, 2 and 3 different redundant switching states, respectively, as listed in Table 2.

Table 2 Switching states and corresponding voltage vectors

Figure 2 Three-level space voltage vector diagram

3 Space Vector Modulation

Similar to the two-level inverter, the three-level space vector PWM modulation also determines the position of the modulation space vector, selects the switching vector to be synthesized, and calculates its corresponding opening time.

We define the voltage space vector modulation of the three-phase three-level inverter as follows

m= （1）

Where: is the modulus of the voltage vector V* rotating in space at an angular velocity ω=2πf;

UD is the module length of the voltage vector V13.

As can be seen from Figure 2, the 24 sectors of the entire vector space of the three-level inverter can be divided into 6 large intervals, and each interval contains 4 small sectors. The rotating voltage vector V* is synthesized by the three voltage vectors Vx, Vy, and Vz in the sector. Their action time is Tx, Ty, and Tz respectively, and Tx + Ty + Tz = Ts. Ts is the switching period. Now define

X= ，Y= ，Z= （2）

Now, taking the first interval (0<θ<60°) as an example, calculate the X, Y, and Z values ​​of Vx, Vy, and Vz corresponding to the rotating voltage vector V* in sectors D1, D7, D13, and D14. Define the boundary conditions of m as Mark1, Mark2, and Mark3, as shown in equations (3), (4), and (5).

Mark1= （3）

Mark2= （4）

Mark3= （5）

1) When the modulation ratio m

(6)

Solving equation (6), we get

（7）

Figure 3 Vector diagram of the rotation vector in sector D1

2) When the modulation ratio Mark1

Solving equation (8), we get

(9)

3) When the modulation ratio Mark2

（10）

Solving equation (10) we get

（11）

4) When the modulation ratio Mmark2

（12）

Solving equation (12), we get

（13）

Thus, when calculating Tx, Ty, Tz of the other five intervals, the calculation of the entire vector space can be realized by replacing the values ​​of θ in equations (7), (9), (11), and (13) with θ-60°, θ-120°, θ-180°, θ-240°, and θ-300°, respectively.

4 Minimum switching loss modulation algorithm

In a three-level inverter, due to the existence of redundant switching states, one voltage vector corresponds to two or three switching states, so a certain algorithm must be used to reduce the number of switching actions, thereby reducing switching losses. The basic principle of the algorithm for reducing switching losses is that each change in the switching state only causes a change in one phase voltage and only the trigger signals of the two complementary switches change, thereby reducing switching losses and reducing the switching frequency. For example, in Figure 2, the space vector rotates from the D14 sector to the D15 sector, and the states of the three-phase switches A, B, and C can change in the order of (221→220→210→110→110→210→220→221)→(221→220→120→110→110→120→220→221). When the space vector V* rotates to the D14 sector, the space vector at this time is synthesized by three vectors V2 (represented by switch state 221 or 110), V7 (represented by switch state 210) and V14 (represented by switch state 220). The modulation order of the switch state in the first bracket is the modulation order of the space vector in the D14 sector. When the space vector V* rotates to the D15 sector, the space vector at this time is synthesized by three vectors V2 (represented by switch state 221 or 110), V14 (represented by switch state 220) and V8 (represented by switch state 120). The modulation order of the switch state in the second bracket is the modulation order of the space vector in the D15 sector. Among them, switch states 221 and 110 represent the same vector V2, which is used as the starting state and the end state of the switch state for transition. Therefore, whether it is inside the sector or between two sectors, every change of the switch state only changes the switch states of the two tubes of the bridge arm complementary drive signal, thereby reducing the switching loss.

5 Experimental studies

The main circuit topology of this experiment is shown in Figure 1. The main switch device of the diode clamped three-level inverter is 2SK1941, which has a maximum withstand voltage of 600V and a maximum on-state current of 16A. The clamping diode is IXY SDESI30, which can withstand a maximum on-state current of 12A. The inverter PWM switching frequency is 5kHz, and the output sine wave fundamental frequency is 278Hz. This digital control system is based on the TMS320F240 DSP chip. The 12 drive signals are generated by the TMS320F240 through the control circuit. The six PWM outputs of the full comparison unit drive the S1 and S3 tubes of the ABC three-phase respectively. The three PWM signals of the single comparison unit and their inverted signals drive the S2 and S4 tubes of the inverter respectively after the dead zone circuit. This control is to transform the sinusoidal AC detection quantity into the dq DC feedback quantity through dq conversion, and then perform PI regulation respectively, and then control the three-level inverter through the SVPWM module. Figure 4 is the control system structure diagram of the three-phase three-level inverter.

Figure 4 Structure diagram of three-level control system

FIG5(a) and FIG5(b) are the experimental waveforms of the output phase voltages VAN, VBN, VCN and the output line voltages VBC, VAC of the diode-clamped three-level inverter, respectively. We can clearly see the shape of the three-level voltage, which is closer to a sine wave than the two-level voltage. Therefore, a lower harmonic distortion rate can be obtained without increasing the withstand voltage of the switch tube and at a relatively low switching frequency.

(a) Phase voltage VAN, VBN, VCN waveform

(b) Line voltage VBC, VAC waveform

Figure 5 Output phase voltage and line voltage waveform (before filtering)

Figure 6 is the waveform and spectrum analysis of the inverter output phase A line voltage when the closed loop is unloaded, with a total harmonic distortion rate of 1.53%. Figure 7 is the waveform and spectrum analysis of the inverter output line voltage and line current when the closed loop is loaded, with a total harmonic distortion rate of 2.75% and a system output power of 1.8kW.

(a) Phase A line voltage waveform

(b) Phase A line voltage spectrum analysis

Figure 6 No-load test waveform and spectrum analysis

(a) Phase A line voltage and line current (1A/100mV) waveform

(b) Phase A line voltage spectrum analysis

Figure 7 Experimental waveform and spectrum analysis under resistive load

From the waveforms in Figures 6 and 7, we can see that the positive and negative waveforms of the closed loop are asymmetric, and the harmonic distortion rate when loaded is higher than when unloaded. This is mainly because when the closed loop is running with load, due to the increase in load current, the current flowing through the midpoint increases, and the inverter keeps charging and discharging the two capacitors on the DC side, resulting in an unbalanced voltage on the two capacitors. In the experiment, there was no special control of the midpoint current, which led to an unbalanced voltage on the two capacitors on the DC side, resulting in an asymmetric positive and negative waveform of the output voltage.

6 Conclusion

The diode clamped three-level inverter increases the number of output levels and makes the output waveform closer to sine through the improvement of its own topology, so the output waveform has a better harmonic spectrum. Since the voltage stress on the switching device is reduced, it is very suitable for high-voltage and high-power applications. In future research, the following two aspects should be paid attention to:

1) The control strategy applied to two levels can be fully implemented in a diode-clamped three-phase three-level inverter. Therefore, some existing waveform control technologies (such as repetitive control technology) can also be tried to be implemented in a three-level inverter.

2) In a diode-clamped three-level inverter, the voltage imbalance of the two capacitors on the DC side is one of the reasons for the deterioration of the output waveform quality. This problem can be solved by voltage feedback compensation or by hysteresis control of the midpoint potential.