High reliability design of engineering machinery remote control based on TMS320LF2407A and NRF903

In the process of rapid economic development in China, construction machinery has played a huge role in promoting the development of the country. However, the environmental conditions at the work sites of traditional construction machinery are generally very harsh, and the workers must operate in a large cab, which can easily cause adverse psychological and physiological effects on the workers, thereby affecting the safe, reliable and efficient operation of the machinery. In recent years, the rapid development of radio communication technology and ultra-large-scale integrated circuits has provided a basis for workers to walk out of the cab and reliably remotely control construction machinery through radio. Since the operation errors of construction machinery can cause huge losses of life and property, reliability is the determining factor in whether wireless remote control technology can be applied to construction machinery.
1 Introduction to construction machinery remote control system
The remote control consists of two parts: the transmitter and the receiver. The operator uses the transmitter to send the control command, which reaches the receiver through the wireless channel. The receiver receives the control command and controls the construction machinery to make corresponding actions [1]. The system block diagram is shown in Figure 1.

The TMS320LF2407A chip is the core control chip of the entire system. NRF903 is the RF transceiver chip of the system. Due to space limitations, this paper focuses on the interface design between TMS320LF2407A and NRF903 and the communication protocol design to carry out high-reliability design of the engineering machinery remote control. 2 Hardware interface design TMS320LF2407A adopts high-performance static CMOS technology, which reduces the power supply voltage to 3.3 V, reduces the power consumption of the controller, and meets the power saving requirements of the handheld transmitter [2]. TMS320LF2407A has good processing performance (40 MIPS), which can realize fast encoding and decoding of control commands and improve the real-time processing and response speed of the remote control to control commands. TMS320LF2407A integrates a variety of peripheral interfaces, such as serial communication interface (SCI) and serial peripheral interface (SPI). These two peripheral interfaces can be easily connected to NRF903. The interface between TMS320LF2407A and NRF903 is shown in Figure 2.

NRF903 is a single-chip RF transceiver chip that operates in the 433/868/915 MHz international ISM frequency band. It has GMSK/GFSK modulation and demodulation capabilities, strong anti-interference ability, and is suitable for industrial control applications [3]. It uses DDS+PLL frequency synthesis technology, has good frequency stability, and has 170 channels, which meets the needs of channel conversion used in this article; it can directly interface with TMS320LF2407A without Manchester encoding the data, and the communication baud rate can reach 76.8 kb/s; the operating voltage range is 2.7 V to 3.6 V, with low power consumption, and few peripheral devices required to form a complete RF transceiver.
3 SPI interface design
3.1 Configuration word design
The synchronous serial port SPI of TMS320LF2407A is used to complete the configuration of the configuration control word of NRF903, set SPI to work in active mode (MASTER/SLAVE=1), and SPICLK outputs a synchronous clock signal to CFG_CLK. Set the serial peripheral interface configuration control register SPICCR = 0x0D. When CS is high, the 14-bit configuration control word from SPISIMO/IOPC2 is written into the configuration register through the CFG_DATA port at each rising edge of the CFG_CLK programming mode clock to complete the setting of parameters such as operating frequency, channel, output power and output clock frequency.
When the configuration control word is input to the data shift register, CS is invalid and a new configuration is completed. The bit rate of CFG_DATA is determined by the baud rate setting register SPIBRR of the SPI module.
Once the configuration is completed, the working state of the chip is set by external signals TXEN, PWR_DWN, STBY and DATA. Except for standby mode and low power mode, the configuration can be completed in all modes, which provides a basis for fast real-time channel conversion [4].
3.2 Channel conversion protocol design for both senders and receivers
This paper adopts the communication channel to switch between three fixed channels to avoid the problem of co-channel interference when using a fixed frequency.
This design uses the 438 frequency band, which has 10 channels available for use. Three of them (channels 0, 4, and 8) are selected to achieve frequency conversion. It is set by CFG_DATA[9~2].
In order to avoid confusion between the channels of the sender and the receiver, this design allows both the sender and the receiver to enter channel 0 when starting up, in standby, or after resetting.
Both the sender and the receiver use flexible channel conversion and channel stay methods to communicate. Each time the transmitter sends a control command on a certain channel, it will wait for a response signal on this channel. If the correct response signal is not received within the specified time, it will automatically switch to the next channel and repeat the above transmission process; if the correct response signal is received within the specified time, it will automatically stay on this channel for a long time, waiting to send other control commands. Each time a correct response signal is received, the transmitter will stay on this channel for a longer time. If there is no correct response signal received after the timeout, it will return to channel 0. The receiver's channel stay method is similar to that of the transmitter, that is, each time a correct command is received, its reception time on this channel will be delayed. However, its channel switching method is different. Its channel switching interval is three times that of the transmitter, to ensure that the channels of the transmitter and receiver are synchronized at most once in nine intervals. The channel switching of the transmitter and receiver is shown in Figure 3. The channel switching process of the transmitter is shown in Figure 4.

If both parties start SPI transmission configuration word to change the communication channel for many times but fail, an overtime interrupt will occur, requiring both the sender and receiver to reset the system to the initial channel 0 state and continue communication. If the system still cannot connect normally after reset, it is possible that all three channels have been interfered. You can manually reconfigure an initial channel for both the sender and receiver so that both senders and receivers can enter another group of channels for communication.
4 SCI module communication design
4.1 Control command coding design
Due to the existence of wireless channel interference factors, the received control instructions are likely to become unreliable. If this control instruction happens to become another group of control instructions, misoperation will inevitably occur. In order to avoid this situation, the difference between different control command codes must be increased. The greater the difference between them, the less likely it is to change from one control instruction code to another, that is, the less likely it is to cause misoperation. This article uses 8 bits to represent a group of control commands, and can get up to 28 = 256 groups of different control commands. Using software programming methods, up to 16 groups of code groups with a difference of 4 bits between different control command codes can be selected, which can represent 16 different control commands and meet the control command number requirements for engineering machinery.
Although this can avoid malfunctions of engineering machinery, it still cannot resist the interference of channel noise on the control command code. If the transmitter is required to resend every time interference occurs, the communication efficiency of the system will be reduced. If the transmitter transmits a control command code with error correction capability, and the receiver performs error correction operations based on the received control command code and coding rules, and automatically corrects the errors that occur during the transmission process, the communication efficiency of the system can be improved to a certain extent. RS coding has a strong error correction capability. This design allows the original control command to appear in the code group in an unchanged form, and adds an RS error correction code after it.
Because the address codes of the sender and receiver are fixed, the original control command code of the sender is fixed, and the RS error correction coding method is used, they can be combined and listed in the memory of the sender TMS320LF2407 A. Each key value corresponds to a different code group in the table. When there is a key action, the table is looked up according to the key value and the corresponding code group is sent. The address code and the original control command code are stored in the receiver's list. The original control command code corresponds to different engineering machinery actions. 4.2 Communication protocol design between sender and receiver The SCI module supports digital communication between the CPU and other asynchronous peripherals using standard formats. The SCI receiver and transmitter are both double buffered, each with its own enable and interrupt flags. The DATA port of NRF903 uses a transparent protocol to communicate, transmitting the received data intact, and can adapt to any standard or non-standard user protocol.

This design selects the SCI module idle line wake-up mode. The idle line mode leaves a fixed space before the address. Initialize SCICCR=07h, select the stop bit as 1 bit, disable parity check, disable self-test mode, select the idle line multiprocessor mode, and the SCI character length is 8 bits. This design uses a frame block to define a control command. The first frame of the frame block is the address frame, which stores the common address of the sender and receiver. Since there are not many engineering machinery operating in the same place, it is sufficient to use 8 bits (to ensure that 28=256 machines work in the same place) to represent the address. The frame block format for implementing a control instruction is shown in Figure 5.

The start bit (0) only occupies one bit and is used to notify the receiving device that a character to be received has begun to arrive. The line should remain at 1 when no characters are transmitted. The receiving end continuously detects the state of the line. If a 0 is detected after a continuous 1, it knows that a new character has been sent and should be ready to receive immediately. Because the design uses a wireless channel, how to make the receiving pin SCIRXD detect continuous 1 in the idle state is a key issue. Since NRF903 has an output pin C_SENSE, when the receiving channel does not receive a carrier, C_SENSE is a stable 0 state; when the receiving channel receives a carrier, C_SENSE becomes 1. According to the characteristics of this pin, after adding a NOT gate to the C_SENSE pin and connecting it to the SCIRXD pin after the data receiving pin of NRF903 through an OR gate (as shown in Figure 2), the above problem can be solved.
Since the communication protocol of the SCI module is not for wireless channels, when it is used in wireless channels, it is necessary to consider how to more effectively utilize the established communication protocol of the SCI module and how to make the established communication protocol of the SCI module tolerate the distortion of the control command after passing through the wireless channel as much as possible so that the communication can proceed normally.
Configure the SCI communication protocol in a programmatic way. Configure the serial communication interface control register 1 SCICTL1 = 0Fh, set the TXWAKE position to 1; write 1 to TXWAKE (SCICTL1.3), and then write data to the SCITXBUF register to generate an idle cycle of 11 data bits; set the SLEEP bit (SCICTL1.2) to 1 so that they are interrupted only when the address byte is detected. When the address read by the processor matches the address of the processor set by the application software, the user program clears the SLEEP bit to ensure that the serial communication interface generates an interrupt when each data byte is received. Set the serial communication interface control register 2 (SCICTL2) to enable the RXRDY/BRKDT interrupt and the TXRDY interrupt. Set the baud rate selection register to determine the transmission rate of the control commands of both the sender and the receiver.
Although the processor can still work when the SLEEP bit is 1, unless the address word is detected, RXRDY, RXINT or any receive error status position cannot be set to 1, and data reception cannot be achieved. The address frame may be distorted after wireless transmission. If the distorted bits of the address frame are within the error correction capability of the RS code, it can be considered as an address frame by the receiver, that is, after a rough judgment of the address frame, the SLEEP bit is cleared to 0 to achieve the reception of the control command frame and the RS error correction frame. The receiving process is shown in Figure 6.

This paper designs and implements the high reliability requirements of the remote control system for construction machinery. However, the overall system also needs to pay attention to the interface design between the operation panel keyboard and TMS320LF2407 A and the interface design between TMS320LF2407A and construction machinery. In order to enable the operator of the remote control of the construction machinery to understand the operation status of the construction machinery more clearly, an LCD can be added to the transmitter of the remote control and some sensors can be installed on the construction machinery so that the transmitter of the remote control can detect the operation status of the construction machinery in real time, thereby further improving its reliability. References [1] Zhao Songjie, Li Lancun. Intelligent remote control of crane based on single-chip microcomputer control. Mechanical and Electrical Engineering, 2008, 25(4). [2] Liu Heping, Deng Li, Jiang Yu, et al. DSP principle and motor control application - based on TMS320LF2407x series. Beijing: Beijing University of Aeronautics and Astronautics Press, 2006. [3] Han Xiangyang, Zhou Fengxing, Hu Lei, et al. Design and implementation of a distance monitoring system based on wireless transceiver module nRF903 [J]. Electronic Measurement Technology, 2006, 29(5). [4] Liu Changhui, He Huahui. Design of 5-32 ton overhead crane remote control device based on single chip microcomputer [J]. Electronic Engineer, 2004, 30(9).