Design and Implementation of CAN Card Based on PCI Bus

The fieldbus CAN (Controller Area Network) is gaining more and more attention and favor due to its high performance, high reliability and unique design. It is not only widely used in the automotive industry, but also rapidly developed in the fields of industrial control, robots, medical equipment, sensors, etc. In order to expand the functions of the CAN bus and connect it to a computer, a CAN adapter card with a CAN interface and a PC interface can be designed to collect information from each node on the CAN bus and forward it to the PC. It can also forward commands and data from the PC to each node and complete partial monitoring and management of the user system on the CAN bus.

The PCI bus is an advanced high-performance 32/64-bit local bus launched by Intel. It can support multiple sets of peripheral devices at the same time, is not restricted by the processor, and has a large data throughput (33MHz bus frequency, 32-bit transmission peak can be up to 132MB/s). At present, PCI is the mainstream computer bus. In the past, CAN cards were generally based on the ISA bus. Due to the low transmission rate of the ISA bus, the CAN card must add a relay control function to adapt to the high-speed transmission of the CAN, resulting in high cost, large size, and low transmission rate, which is not conducive to the promotion and application of the CAN bus. Because the PCI bus has a fast transmission speed and supports hot plugging, power management and other functions, it can not only meet the high-speed data transmission of the CAN bus, high performance, strong functions, but also small size, low price, easy to use, and wide range of applications.

The design of CAN card includes hardware design and software design.

1 Hardware Design

The PCI bus is a local bus independent of the CPU, different from the traditional ISA bus. Since the PCI bus specification defines strict electrical characteristics and timing requirements, the development difficulty is greater than that of the ISA bus. There are generally two solutions to implement the PCI interface: using programmable logic devices and dedicated bus interface devices. The biggest advantage of using programmable logic devices to implement the PCI interface is that it is more flexible, and the PCI timing module and functional module can be combined together. There are also many devices that can be used (such as Altera's CPLD devices, Xilinx's FPGA devices, etc.). You can also buy PCI core design modules compiled by manufacturers using hardware description languages ​​such as VHDL and AHDL. However, its design difficulty is still very high, because the PCI bus has strict requirements on load requirements and the establishment time of transmission data. At the same time, it is also necessary to implement various registers for configuration inside the device, as well as registers for completing logic verification, address decoding, etc. (roughly 15,000 gate circuits). In addition, FIFO, user register group and back-end device interface need to be added. Designing this PCI bus interface will result in a large amount of manpower and material resources being invested in complex logic verification and timing analysis, and the development cycle is long. Although the use of dedicated interface devices is not as flexible as the use of programmable logic devices, it can effectively reduce the difficulty of interface design and shorten the development time. Dedicated interface devices have low cost and high versatility, can optimize data transmission, provide configuration space, have on-chip FIFO for burst transmission function, provide extended local bus and other advantages, and many companies also provide supporting development tools (such as evaluation boards or driver development software), which are very convenient to use and have a short development cycle. Currently, PCI bridge chips from companies such as PLX, AMCC, and Cypress are common on the market. The general characteristics of various types of PCI interface chips are shown in Table 1.

PCI devices can be divided into master mode and slave mode. The master mode bridge chip can perform DMA operations, while the slave mode can only accept read and write operations. According to the transmission data bandwidth (maximum 132MB/s) provided by PCI and the requirements of CAN bus (maximum 1Mbps), coupled with economic and development difficulty and cycle considerations (master mode bridge chips are more expensive and more difficult to develop), and because DMA function is not required, the use of slave mode bridge chips is sufficient to meet the needs of data transmission. In addition, the selection of chips not only considers performance and economic requirements, but also the difficulty of hardware development and driver development. If sufficient chip descriptions, application samples and development tools are not provided, the development difficulty will be greatly increased and the development cycle will be extended. Therefore, the PCI bus target interface chip PCI9052 of PLX Company is used as the PCI interface chip in the CAN card, responsible for data communication with the computer.

PCI9052 is a low-cost PCI bus slave mode interface chip developed by PLX. It has low power consumption and complies with PCI2.1 specification. The local bus (Local Bus) provided can be programmed as an 8/16/32-bit (non-) multiplexed bus. Its main features are:

(1) Direct data transfer mode PCI9052 supports PCI to Local Bus memory mapping and I/O mapping burst read and write.

(2) ISA interface logic PCI9052 supports single-cycle read and write access from PCI to ISA bus through 8/16-bit memory mapping or I/O mapping, facilitating the conversion from ISA card to PCI card.

(3) The interrupt generator can generate a PCI interrupt signal: INTA# from the two interrupt signals of the Local Bus.

(4) Local bus The local bus provided by PCI9052 is not only programmable, but also runs independently of the PCI bus clock, which can realize asynchronous operation, and the bus operation automatically realizes timing synchronization. The asynchronous operation of the two buses facilitates the compatibility of high-speed and low-speed devices. The local operating clock frequency range is 0-40MHz, TTL level, which can be provided by PCI or provided by the user; the operating clock frequency range of PCI is 0-33MHz.

(5) Serial EEPROM is used to store some configuration information of PCI BUS and Local Bus.

(6) The four local device chip select base addresses and address ranges can be set by the serial EEPROM or the master control device.

(7) The base addresses and address ranges of the five local address spaces and their mapping can be set by the serial EEPROM or the master control device.

(8) Byte swapping in Big/Little Endian mode is suitable for different computer systems.

(9) Local Bus Wait State In addition to the wait signal LRDYi# for handshake, PCI9052 also has an internal wait generator (including waits for address to data cycle, data to data cycle and data to address cycle).

(10) Delayed Read Mode PCI9052 supports the delayed read mode of the PCI2.1 specification.

(11) FIFO PCI9052 includes a 64-byte write FIFO and a 32-byte read FIFO, thus supporting prefetch mode, i.e. burst operation.

(12) PCI Locking Mechanism The master device can obtain sole access to PCI9052 through the locking signal.

Due to the rapid development of CAN bus, many chip manufacturers have developed many series of CAN communication controller chips, as shown in Table 2.

Since PCI9052 can start the reading and writing of the local bus, the CAN card no longer needs a microcontroller, and a CAN communication controller can be used. This CAN card uses SJA1000. SJA1000 supports BasicCAN and PeliCAN modes, has FIFO, supports hot plugging and other functions, can not only realize the CAN bus interface function, but also the chip can output a programmable CLKOUT signal according to the frequency of the crystal oscillator, which can be used as the bus frequency of the local bus of PCI9052, saving devices and facilitating design. The bus frequency of the CAN bus can be 12MHz, 16MHz or 24MHz, and PCI9052 automatically synchronizes the access of the local bus and the PCI bus. The CAN bus transceiver uses 82C250. This chip is the interface between the CAN bus controller and the physical bus, can provide differential transmission and reception capabilities for the CAN bus, has the ability to resist instantaneous interference and protect the bus, and can reduce radio frequency interference by adjusting the edge slope of the communication pulse on the CAN bus.

Since the hardware resources of PCI devices in the computer are dynamically allocated by the system, after designing the basic hardware framework, PCI configuration design should be carried out. The hardware resources of the CAN card are the memory mapping space that maps the internal registers of SJA1000 and an interrupt source. PCI9052 provides 5 local address spaces, one of which can be selected as the address space of SJA1000, and 32 8-bit addresses are allocated. At the same time, the corresponding initialization is set, the register PCIBAR2 in the PCI configuration register is set to 0XFFFFFFE0, the number of memory allocated to the system is 32, the type is not pre-read, and the values ​​of other registers can be set to 0. Set the range of the local address space to 0X00000000~0X00000020. PCI9052 provides 2 local interrupt sources, which can be used by LINTi1. Note that: the LINTi1 signal line has no driving capability, and the INT pin of SJA1000 has no driving capability, so the signal line must be added with a pull-up resistor, otherwise the level of the signal line is uncertain and the work is definitely not normal. SJA1000 provides a level-triggered interrupt signal, so the interrupt trigger mode of PCI9052 is set to level trigger. The local device chip select CS0# of PCI9052 is used as the chip select signal of SJA1000. The starting address and address range of the CS0# chip select signal are set by the CS0 Base Address register, and the value is 0X00000002. In addition, the LRDYi# signal of PCI9052 is the local bus data preparation signal. The register address of SJA1000 is mapped to the address. There is no delay in data transmission, so the LRDYi# pin can be grounded, indicating that the register of SJA1000 is always immediately readable and writable. The initial value of the PCI9052 register is provided by the serial EEPROM and is read after the PCI9052 is powered on. The EEPROM must use a chip that supports the continuous reading function. This design uses Microchip's 93LC46B. The development tool PlxMon provided by PLX can be used to read and write 93LC46B.

PlxMon can be used for hardware debugging of PCI9052. It can be used to check the configuration resources of PCI devices. Using the SDK provided by PLX, the local registers, local bus and EEPROM of PCI9052 can be read and written, so that the hardware can be debugged. With the help of development tools, there is no need to develop debugging software for PCI devices, which can save a lot of time. At the same time, SDK also provides a program framework for the development of driver programs, which speeds up the development progress.

2 Software Design

Software design includes driver design and COM component programming.

Since the interrupt, I/O port, mapped memory and other resources of PCI devices are dynamically allocated, it is necessary to write a driver to manage the hardware before it can be used by users for programming. For the sake of versatility and compatibility, the development of the CAN card driver adopts a WDM driver that supports Windows XP, Windows 2000 and Windows 98. The development tools use Visual C++6.0 and Win2000 DDK. Since there is no microcontroller on the CAN card, all operations on the CAN bus port are completed by the driver. This not only allows the computer to implement complex functions, such as error detection, breakpoint continuation, etc., but also saves hardware and is conducive to the upgrade of the CAN card - just replace the driver. The main functions of the driver are to configure the CAN interface of SJA1000, send and receive data on the CAN bus, monitor the CAN bus in real time, and receive the send and receive commands of the user program. The sending and receiving of data and CAN bus errors are all handled by interrupts. The driver can respond quickly and directly notify the user program through the event kernel object. Since the WDM driver runs in the kernel state of the system, it is very complicated to write. Due to space limitations, only the block diagram of the software is given (see Figure 2).

The circuit block diagram of the CAN card is shown in Figure 1.

In order to facilitate the use of users, corresponding API functions or other application layer programs such as ActiveX controls should also be written and provided to users. Since ActiveX controls are based on advanced COM technology, they have good encapsulation and flexibility, which can make user programming simple and convenient. Therefore, ActiveX controls are written in the design of CAN cards. ActiveX controls are responsible for communicating with the driver, notifying the user program of the data received by the CAN card through the control's events, setting the CAN communication controller using the control's properties, and sending the user program's data according to the set method.

According to the above design, a CAN card named Can1000 was developed. It has been proved that the card has simple and clear design, high performance, low cost, easy to use driver and ActiveX control, and meets the requirements of design and users.