Utilize parallel port to realize high-speed data communication with DSP in EPP mode

    Abstract: High-speed data communication between DSP and PC is an important application of DSP. This article analyzes the principle of high-speed data exchange between the parallel port in EPP mode and ADSP21060, and discusses in detail the structure diagram of its hardware design and its corresponding parallel port programming.

    Keywords: computer parallel port EPP DSP FIFO

With the advancement of technology and the increase of a large number of peripherals, the computer parallel port is not only required to connect to the printer, but also to other peripherals, and is required to be able to transmit data in both directions. High-speed peripherals also require high-speed data transmission, such as DPS. Today, with the rapid development of science and technology, the processing power and speed of DSP are also rapidly improving, and it is widely used in electronic fields such as scientific research, military and communications. In these applications, high-speed data transmission with the PC is inevitable. The traditional transmission mode of computer parallel port is SPP (standard parallel port). The data transmission direction is from the computer to the peripheral device. Data can only be output, not input. This limits the application of parallel port high-speed data communication. So we designed a solution to realize high-speed data transmission between DSP and PC in EPP mode.

Implement data transmission in EPP mode

The EPP protocol is a protocol that is compatible with the standard parallel port and can complete two-way data transmission. The parallel port defined by this protocol is more like an open bus, providing users with powerful functions and flexible design means.

It has four data transmission cycles: data write cycle; data read cycle; address write cycle; address read cycle. The data cycle is used to transmit data between the host and peripherals, and the address cycle is generally used to transmit address, channel, command and control signals. This causes the cycle to be viewed as two different data cycles.

One of the most important features of the EPP mode is that the entire data transfer process occurs within an ISAI/O cycle. In other words, using the EPP protocol to transmit data, the system can obtain a transmission rate of 500K-2M bytes/second, that is, the parallel port peripherals have performance close to that of the ISA bus plug-in board. Using an interlocked handshake signal, data transmission is determined by the slowest device in the interface, which can be either a host or a peripheral. This "rate adaptability" is transparent to both the host and the peripheral. All parallel port transmission methods utilize interlocking handshake signals. In this way, the peripheral device can control the settling time required for its own operation. At the same time, because the process of data transmission in EPP mode is simple and easy to implement, we decided to use the bidirectional parallel port EPP transmission mode to achieve high-speed data transmission.

When the parallel port transmits data to the DSP chip ADSP21060 of Analog Devices, a byte of data is latched through the data latch, and then an interrupt signal is given to the ADSP21060 to read the data; similarly, when the ADSP21060 transmits data to the parallel port, it first Let the latch lock the data, and then give the parallel port an interrupt to read the data. This completes the two-way communication of data. However, using this method, no matter which direction the data is transmitted, only one byte can be transmitted and an interrupt will be caused, which will then be read by the PC or ADSP21060, and then the next byte will be transmitted, which takes up a lot of CPU time. time, reducing the efficiency of the CPU. For this reason, we use two FIFOs to improve the efficiency of the CPU.

High-speed data transmission based on FIFO in EPP mode

The principle block diagram of high-speed data communication based on FIFO in EPP mode is shown in Figure 1.

Its communication process is: when the parallel port transmits data to ADSP21060, the parallel port first resets the output FIFO, then writes the data to be transmitted in batches to this FIFO and then gives an interrupt signal to ADSP21060 to notify it to read data from the output FIFO. ;

When the ADSP21060 transmits data to the parallel port, it first resets the input FIFO, and then writes the data to be transmitted into the FIFO in batches and then gives an interrupt signal to the computer parallel port to notify it to read the data from the input FIFO, thus completing the data processing. Two-way communication.

This design has the advantage of transmitting data in blocks, and at the same time, it takes up very little time on the parallel port and ADSP21060 when transmitting large amounts of data.

The main logical relationships in the figure are as follows:

Output FIFO read (AR) = RD and A0 and A1 and MS01;

Output FIFO write (PW) = nWrite or nDstrb;

Input FIFO read (PR) = not (nWrite) or nDstrb;

Input FIFO write (AW) = WR and A0 and A1 and MS01.

In this circuit design, there are two issues worth noting:

(1) The nWait signal needs to be generated through the logical relationship between nDstrb and nAstrb. The logical relationship is: nWait=not (nDstrb and nAstrb).

(2) Since EPP and SPP are compatible, in EPP mode, the bits corresponding to nWrite and nDstrb format nAstrb in the parallel port command word need to be set to invalid.

Computer EPP parallel port programming

The electrically programmable logic device (EPLD) we chose is Altera's EPM7128. For a detailed introduction, please refer to Altera's device manual. Here we only give the control program written in AHDL language as follows:

FIFO memory clearing subroutine, send a clearing pulse to FIFO: void fifo_rst(void); set command word subroutine: void command(void); write data to FIFO subroutine: void data_out (void); read data from FIFO Subroutine: void data_in(void);

Before accessing the EPP register, the software must write zeros to bits 0, 1, and 3 of the control register; when writing data, write the number of data in the pointer ptr into the output FIFO memory through the data port, and then cause the ADSP21060 interrupt; when reading data Read number from the input FIFO memory through the data terminal and then read the data into the pointer ptr.

#define BASE_ADDR 0X378

#define ADDR_PORT 3

#define DATA_PORT 4

#define CONTROL_PORT 2

#define CONTROL_ININT 2

#define SET_BIT(x,b) ((x)=(1<<(b)))

#define CLEAR_BIT(x,b) ((x)&=～(1<<(b)))

void fifo_rst()

{

char control;

vontrol=inportb(BASE_ADDR+CONTROL_PORT);

CLEAR_BIT(control,CONTROL_ININT);

outportb (BASE_ADDR+CONTROL_PORT,control);

SET_BIT(control,CONTROL_ININT);

outportb (BASE_ADDR+CONTROL_PORT,control);

}

void command(void)

{

int com;

com=0;

control=inportb(BASE_ADDR+CONTROL_PORT);

control=control & oxf4;

outportb(BASE_ADDR+CONTROL_PORT,control);

}

void data_out(int number,char *ptr)

{

int i;

fifo_rst();

for(i=0;i

outportb(BASE_ADDR+ADDR_PORT,0);

}

void data_in(int number,char *ptr)

{

int i;

for(i=0;i

}

in conclusion

This article gives an implementation plan for high-speed data communication using FIFO and ADSP21060 in EPP mode. This circuit can complete high-speed data transmission between the ADSP21060 and the computer parallel port, and takes up very little time on the ADSP21060 and the computer. In addition, the subroutines compiled in this article have reference value for other circuits that perform high-speed data communication with PCs. Debugging proves that this solution is feasible.