Application of DSP in mobile communications

    Abstract: Programmable DSP (Digital Signal Processor) has been widely used in digital telephones. This article explains the application of DSP in current standards and looks forward to the future development trend of DSP in the direction of low power consumption.

    Keywords: DSP mobile communication low power consumption

There are currently two main trends in mobile terminal structures. One is to face the changing standards and emphasize the flexibility of using programmable DSP; the other is to emphasize the efficiency achieved with application-specific integrated circuits (ASICs). In the future these two aspects will surely be combined.

Application of DSP in GSM

The functional block diagram of GSM is shown in Figure 1. A typical digital communication module in the figure includes: signal compression, error detection, encryption, modulation and equalization. Initially, it was thought that low power consumption requirements meant that most GSM terminals would be implemented with ASICs, but with the development of technology, the difference in power consumption between DSPs and ASICs became less important.

In GSM phase 1, the encoder uses RPELTP (short pulse excitation linear pre-warm coding) technology to compress speech to 13Kb/s. Most hardware engineers believe that the speech encoder should be implemented by DSP. Moreover, once the DSP application is engaged in the task of "continuous upgrading", it becomes more powerful. Now the DSP begins to assume other functions of the physical layer in the functional diagram shown in Figure 1.

Flexibility is very important in evolving standards. GSM Phase 2 introduced enhanced full rate (EFR) and half rate (HR) voice coding. Half rate achieves the same voice quality with a higher compression rate of 5.6Kb/s, but at the cost of increased complexity. Enhanced full rate can provide better voice quality and performance at the cost of higher complexity, which is achieved by applying an algorithm called Vector Sum Excited Linear Prediction (VSELP).

With these changes, the performance of the physical layer is getting better, the cost is getting lower, and the power is more economical. Therefore, the physical layer of each generation of mobile terminals has some slight differences from the previous generation, and the upgrade of ASIC-based solutions is more difficult and costly. Because there are now low-power DSPs designed specifically for wireless applications, the power saved by using ASICs to implement the functions completed by DSPs is not enough for system designers to give up the flexibility of using DSP designs. After 1994, the function of a single DSP chip has become very powerful, and even all functions of the baseband can be realized with a single DSP chip. In order to save power and reduce the size of the circuit board, several DSP chips, such as Motorola56652 and TI's digital baseband platform, integrate RISC (reduced instruction set computer) microcontrollers to handle protocols and human-machine interfaces, so that the DSP can Specialize in the task of communication algorithms.

With the evolution of GSM mobile terminals, it has gradually developed to not only implement simple telephone functions, which allows DSP to be used not only in the physical layer but also in other layers. Especially with the arrival of the third generation of mobile communications and the application of wireless data services, this trend will accelerate.

The trend of DSP development towards low power consumption

The enhanced structure, design and processing capabilities of the new generation of DSP provide better performance and lower power consumption, making it suitable for battery-powered applications. We know that many communication algorithms are multiply and accumulate (MuAcc) operations, which consist of taking two operands from memory, performing a multiplication and accumulation, and then putting the result back into memory. So we use mW consumed per million MuAcc to evaluate DSP power consumption. According to statistics, current DSP power consumption is reduced by half every 18 months. Due to the static logic used by DSP, the main power consumption is the charging and discharging of the internal capacitance of the device. This dynamic power consumption is shown in the following formula:

p=ac×V swing ×V power ×f

In the above formula, P represents the power consumed, a represents the number of cycles of the internal node in each clock cycle, the v swing is equal to the v power supply, and f represents the frequency. The dynamic power consumption of the entire chip is the sum of P of all nodes in the circuit. From the above equation, we can see that since the dynamic power consumption of each node is proportional to the square of the supply voltage, reducing the supply voltage is very important to save power. For example, reducing the supply voltage from 3.3V to 1.8V reduces power consumption by 3.4 times. However, just reducing the supply voltage without improving the technology is incomplete. Therefore, while reducing the supply voltage, technology must be improved to improve performance and reduce power consumption.

Let's take TI's TMS320C54x as an example to introduce its low-power design. TMS320C54x is a DSP chip specially designed for wireless communication applications. In addition, with the continuous growth of the wireless market, several other DSP chips specifically designed for wireless applications have appeared on the market, such as Lucent's 16000 series and ADI21xx series.

The structure and instruction set of the C54x are designed to save power. C54x uses an improved Harvard architecture, with three data storage buses, a program storage bus, two data address generators and a program address generator. This structure allows simultaneous access to numbers and is suitable for multi-operand operations, thereby reducing the number of cycles required to complete the same function.

Another strategy used by the C54x to save power is to add special instructions that can execute important algorithms in wireless applications. For example, the shifter and exponent detector of the arithmetic logic unit in C54x enable single-cycle execution of various numerical operations, and the exponent encoder supports floating point operations for speech encoding. There is also a comparison selection storage unit (CSSU) that greatly speeds up Viterbi decoding.

The C54x instruction set also contains several dedicated instructions, including: single instruction repetition and instruction block repetition, conditional instructions, Euclidean distance calculation, FIR (finite impulse response) and LMS (least mean square) filter operation instructions, etc. All in all, it is convenient to currently use DSP to complete VSELP in the IS-54/136 standard, which consumes 7.4mW power and consumes 1.3mW power when GSM voice encoding.

Power management is very important in low-power DSPs. C54x applies a hybrid power management strategy, which is active internal clock control and three user-controlled idle modes: shut down the CPU, shut down the CPU and on-chip peripherals, and only maintain memory status of the entire device. The combination of a digital phase-locked loop-based clock generator and a clock generator allows the user to optimize the frequency and power consumption of the application.

Application and structure of future mobile energy and communication devices

Since cellular communications were commercialized in 1983, there have been several development trends. The most important one is the development from analog to digital, which has increased the capacity of the system and the number of users. The use of digital technology has driven the development of mobile terminals from the initial voice function to a variety of data services in addition to voice. Especially with the current rapid development of the Internet and the trend of evolving to the third generation of mobile communications, mobile user data services will include multimedia services such as images, voice, data, etc. The development of these businesses has strengthened the requirements for signal processing, which drives the demand for powerful DSPs.

A traditional cellular phone with a dual-processor architecture is actually a simple modem. In the future, terminals focusing on data services will have a new structure, which must increase processing resources to support increasingly complex user interfaces and handle more complex data services and more complex application environments in addition to voice. Among them, one solution is a DSP core plus a coprocessor structure, and the other structure is multiple DSPs plus additional hardware to accelerate complex processing.

In short, the issues that future mobile devices centered on data services need to consider are: user-friendly interface, low system power consumption, uncomplicated software and short time to market. Programmable DSP will provide power-effective processing and support flexible applications and upgrades. Therefore, low-power DSP will be more widely used in future mobile communications.