Abstract: TL16C750 is an asynchronous communication chip produced by TI. When the real-time requirements of the communication system are high, the system's high-speed serial communication can be achieved by extending the asynchronous communication chip TL16C750, thereby enhancing the system's communication interface control capability. This article introduces the performance of TL16C750 and the registers related to communication, and gives the hardware application circuit of TL16C750 in the communication system between TMS320C50 and PC and the software programming of TMS320C50 to initialize TL16C750.
Keywords: digital signal processing communication interface extension asynchronous communication TL16C750
General-purpose digital signal processors (DSPs) are widely used in high-speed digital signal processing due to their strong data processing capabilities, but their communication interface control capabilities are relatively weak. For example, TMS320C50 has two serial ports, one of which is TDM (Time Division Mulitipl), and the other serial port is often occupied by the voice interface. When TMS320C50 independently constitutes a processing unit, it often needs to exchange some data with peripherals, and weak communication capabilities will affect the application of DSP. When developing a speech signal spectrum analyzer, the author uses TMS320C50 as the signal processing unit to perform Fast Fourier Transform (FFT), and then transmits the conversion results to a PC through the serial port for display or further processing. Due to the high real-time requirements of the system, how to achieve high-speed and reliable communication between TMS320C50 and PC becomes even more important.
1 Asynchronous communication chip TL16C750
For TI's (Texas Instruments) TMS320 series digital signal processors, there are generally two methods of designing a serial port: the first is to use the general I/O port line XF and BIO to form a serial port, which is set by software. Baud rate, this method is often used when the DSP is not busy; but when these two I/O lines are occupied or the real-time communication requirements are high, the DSP should implement high-speed serial communication by expanding the asynchronous communication chip. line of communication.
TL16C750 is an asynchronous communication chip from TI. Its main features are as follows:
●Pin compatible with TL16C550B/C;
●The 16-byte or 64-byte FIFO can be set by software to reduce CPU interrupts;
●The baud rate can reach up to 1M, and its baud rate generator is programmable;
●Programmable serial data sending format:
The data bit length is 5, 6, 7, 8;
With even parity, odd parity or no parity mode;
Stop bit lengths are 1, 1.5, 2;
●Adopts 44-pin PLCC (Plastic Leaded Chip Carrier) package.
1.1 Pin functions of TL16C750
The pin diagram of TL16C750 is shown in Figure 1. The function description of each main pin is as follows:
A0~A2: On-chip register selection signals;
D0~D7: bidirectional 8-bit data lines;
CS0, CS1, CS2: Input chip select signals. When CS0=CS1=1 and CS2=0, TL16C750 is selected;
ADS: It is the address strobe signal. When this pin is valid, CS0, CS1, CS2 and A0, A1, A2 can be latched inside the TL16C750;
XIN, XOUT: external clock terminal, these two pins can be connected to crystal oscillator or external clock signal;
RXRDY is a ready-to-receive signal. When the TL16C750 has received a character from the serial input terminal, this signal is invalid and can be used as an interrupt request signal in interrupt mode;
TXRDY is a ready signal to send. When the TL16C750 allows sending and the sending buffer is empty, this signal is valid and can be used as an interrupt request signal in interrupt mode.
1.2 On-chip registers of TL16C750
There are 11 registers inside the TL16C750. These registers are used to implement functions such as setting communication parameters, accessing the status of lines and MODEN, sending and receiving data, and interrupt management. Programmers can access or control any register of the TL16C750 through multiplexing through the three on-chip register selection lines A0, A1, and A2 and the division latch access bit DLAB of the line control register. Table 1 shows the status of DLAB and A0, A1, and A2 when accessing these registers. Because the DLAB, A0, A1, and A2 bits of the receive/transmit buffer register are all the same, they must also be distinguished by read/write signals: when the chicken uses the IN instruction, the receive buffer register is accessed, and when the chicken uses the OUT instruction, the transmit buffer The register is accessed.
The following is a brief introduction to the registers related to the communication between TMS320C50 and PC.
Table 1 On-chip registers of TL16C750
DLAB | A2 | A1 | A0 | register |
0 | L | L | L | receive/transmit buffer register |
0 | L | L | H | Interrupt enable register |
X | L | H | L | Interrupt identification register |
X | L | H | L | FIFO control register |
X | L | H | H | line control register |
X | H | L | L | MODEN control register |
X | H | L | H | line status register |
X | H | H | L | MODEN status register |
X | H | H | H | scratchpad |
1 | L | L | L | Baud rate factor register low bit |
1 | L | L | H | Baud rate factor register high bit |
The line control register (LCR) is used to store the binary serial data format transmitted through the serial port. LCR is an 8-bit register. The definitions of each bit are as follows: d0d1 is the word length selection bit. If d0d1=00, the transmitted word length is 5 bits. ; When d0d1=01, the word length is 6; when d0d1=10, the word length is 7; when d0d1=11, the word length is 8. The d2 bit is the stop bit selection. When d2=0, the stop bit is 1 bit; when d2=1, the stop bit is 1.5 bits. The d3 bit is the valid check bit. When d3=0, the check is valid; when d3=1, the check is invalid. d4 is the parity type bit. When d4=0, odd parity is performed; when d4=1, even parity is performed. The d7 bit (DLAB) is the lock baud rate generator bit. When d7=1, access the baud rate factor register; when d7=0, access other registers.
The Line Status Register (LSR) is used to record status information of the serial data transmission and reception process, and the CPU can read this information at a collective time. The status bits of this register are listed in Table 2.
Table 2 Status bits of TL16C750 register
Everyone from LSR | 1 | 0 |
d0 reception completed mark | Receiving completed | Reset after reading |
d1 receives overlap flag | overlap occurs | Reset after reading |
d2 parity error flag | Parity error | Reset after reading |
d3 format error flag | Error in receiving | Received correctly |
d4 discontinuity flag | Received 0 consecutively | uninterrupted |
d5 sends buffer empty flag | THR is empty | Write THR to reset |
D6 sends shift register empty flag | Empty | Not empty |
d7 receiver FIFO error | FIFO is wrong | FIFO error free |
Two 8-bit baud rate factor registers can form a 16-bit baud rate factor register. The TL16C750's internal baud rate generator generates the clock signal for sending data. The baud rate factor can be found using the following equation:
Baud rate factor = base clock frequency / (16 × baud rate)
This baud rate generator can generate standard baud rates using three different frequencies that are relatively common. The three different frequencies are 1.8432MHz, 3.072MHz and 8MHz. You can arbitrarily choose the order of writing the high byte and low byte of the baud rate factor, but the d7 (DLAB) bit of the line control register (LCR) must be set to 1 before writing. D7 of the line control register should be restored to 0 after writing the baud rate factor in order to access other registers. When the external crystal oscillator is 1.8432MHz, the values of the baud rate factor register corresponding to several commonly used baud rates are listed in Table 3.
Table 3 The value of the baud rate factor register corresponding to the baud rate factor
baud rate | Baud rate factor register value |
3600 | 32 |
4800 | twenty four |
9600 | 12 |
19200 | 6 |
38400 | 3 |
2 Hardware circuit for serial communication between TMS320C50 and PC
The hardware circuit for communication between TMS320C50 and PC is shown in Figure 2. In the figure, CS0 and CS1 of TL16C750 are connected to high level, while CS2 is connected to IS of TMS320C50. IS is the external I/O space selection line of TMS320C50. It determines the space accessed by the CPU together with PS (program space selection) and DS (data space selection). When TMS320C50 uses IN and OUT instructions to access the internal register of TL16C750, the IS signal is valid and TL16C750 is selected.
When the XIN,
The data lines D0~D7 of TL16C750 are directly connected to the D0~D7 data lines of TMS320C50; the on-chip register selection lines of TL16C750 are connected to A0~A2 of TMS320C50.
Since the typical value of the read signal and write signal retention time of TL16C750 is 40ns, the WR and RD of TMS320C50 can be directly connected to the WR1 and RD1 of TL16C750. In order to avoid conflicts with other I/O ports, in the hardware circuit design , connect the RD signal line of TMS320C50 and the two high-order address lines A15, A14 and IS through a NAND gate and then connect them to the RD1 end of TL16C750. Practice has proved that such a design can also improve write signal performance to a certain extent on the basis of solving address conflicts. The read signal of TMS320C50 is also processed similarly. The specific circuit is shown in Figure 3.
Since the RS-232-C circuit level is different from the CMOS level, the RS232 driver must undergo level conversion when connected to the CMOS level. This system uses the MAX3232 to accomplish this function. The MAX3232 has a proprietary low-dropout transmitter output stage that provides true RS-232 performance when powered by a dual charge pump 3.0~5.5V. This device requires only four small external capacitors of 0.1 μF and can ensure operation at a data rate of 120kb/s while maintaining the RS-232 output level, so it is very suitable for high-speed serial data communication situations. The serial input line (SIN) and serial output line (SOUT) of TL16C750 are connected to R1OUT and T1IN of MAX3232 respectively. After level conversion, T1OUT and R1IN of MAX3232 are connected to the serial port of the PC.
Although TL16C750 and TMS320C50 can work through query, this will reduce the performance of the system. The author uses RXRDY and TXRDY to introduce external interrupts in this system, so that the system works in interrupt mode, thus ensuring high-speed communication between TMS320C50 and PC. As can be seen from Figure 2, RXRDY will generate an external 0 interrupt (INT0), and TXRDY will generate an external 1 interrupt (INT1).
3 Software design
The system software design includes the initialization and communication protocols of the PC, TMS320C50 and TL16C750. The following will give the program for TMS320C50 to initialize TL16C750 based on the hardware of this system. The main task of initialization is to set the parameters required for operation. These parameters include the number of data bits, stop bits, parity, etc. of the data string during serial communication. In addition, you also need to set the baud rate and interrupt mode of sending and receiving.
In this system, the address of the line control register (LCR) of TL16C750 is 8003H (A15=1, A14=0). The baud rate is set to 38400, the high bit of the baud rate factor register is 00H, and the low bit is 03H. The communication format is 8 data bits, 2 stop bits, odd parity, and the value of the line control register (LCR) is 07H. The system works in interrupt mode and should allow receiving ready interrupts and sending buffer empty interrupts. Correspondingly, the value of the interrupt enable register is also set to 03H. The specific program is as follows:
TEM-BUF EQU 80H
AORG 40H
INIT-TL16C750 ROVM
LACK 80H; DLAB=1, set the baud rate
SACLTEM-BUF
OUT TEM-BUF, 8003H
LACK 00H; baud rate 38400,
SACL TEM-BUF; the value of the 16-bit baud rate factor register is 0003>
OUT TEM-BUT, 8001H
LACK 03H
SACLTEM-BUF
OUT TEM-BUF,8000H
LACK 07H; communication format setting, 8-bit data
SACL TEM-BUF; 2 stop bits, odd parity
OUT TEM-BUF, 8003H
LACK 03H; Set interrupt enable register
SACLTEM-BUF
OUT TEM-BUF, 8001H
4 Conclusion
When TMS320C50 communicates with a PC through the extended serial port, its hardware interface is simple, the data transmission distance is long, and it is economical to use. This circuit and its software have been proven by the communication practice with the microcomputer to achieve reliable communication with the PC at the baud rate of 38400.
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